C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 200

• Manufacturer Part Number: C8051F320-TB
• Description: BOARD PROTOTYPING W/C8051F320
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320-TB

• Contents: Board
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F320
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F320/1
slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex
operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave
mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK,
NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less
than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to
the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can
receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided
that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.
200
NSS (Must Remain High
in Multi-Master Mode)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MISO
NSS (4-Wire Mode)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0)
Figure 18.5. Master Mode Data/Clock Timing
MSB
MSB
MSB
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Rev. 1.4
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 0
Bit 0
Bit 0