C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 23

• Manufacturer Part Number: C8051F320-TB
• Description: BOARD PROTOTYPING W/C8051F320
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320-TB

• Contents: Board
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F320
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.7.
The C8051F320/1 Family includes an SMBus/I
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.8.
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programma-
ble capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8. The external clock source selection is useful for real-time
clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the
system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
Serial Ports
Programmable Counter Array
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
PCA
CP0
CP1
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0)
Figure 1.7. Digital Crossbar Diagram
2
4
2
2
2
6
2
8
8
8
8
2
C interface, a full-duplex UART with enhanced baud rate
Rev. 1.4
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
8
8
8
1
PnMDIN Registers
PnMDOUT,
Cells
Cells
Cells
Cells
Note: P2.4-P2.7 only available
P0
I/O
P1
I/O
P2
I/O
P3
I/O
on the C8051F320
C8051F320/1
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
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