C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 58
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F320/1
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and supply current falls to less than 100 nA. See Section “14.1. Priority Crossbar Decoder” on page 128
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally
driven from –0.25 V to (V
ifications are given in Table 7.1.
Comparator response time may be configured in software via the CPTnMD registers (see Figure 7.3 and
Figure 7.6). Selecting a longer response time reduces the Comparator supply current. See Table 7.1 for
complete timing and supply current specifications.
58
CMX1N1
CMX1N0
CMX1P1
CMX1P0
Note: P2.6 and P2.7 available
only on C8051F320
P1.2
P1.6
P2.2
P2.6
P1.3
P1.7
P2.3
P2.7
Figure 7.2. Comparator1 Functional Block Diagram
DD
) + 0.25 V without damage or upset. The complete Comparator electrical spec-
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1OUT
CP1RIF
CP1FIF
CP1EN
CP1 +
CP1 -
CP1MD1
CP1MD0
CP1RIE
CP1FIE
Rev. 1.4
+
-
VDD
GND
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Rising-edge
CP1
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP1
CP1A
CP1
CP1
CP1RIE
CP1FIE
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