C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 217
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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19.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or USB Start-of-Frame (SOF) capture
mode. The Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3) and T2SOF (TMR2CN.4) bits.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
19.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT = ‘0’ and T2SOF = ‘0’, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 19.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
External Clock / 8
SYSCLK / 12
SYSCLK
T2XCLK
0
1
Figure 19.4. Timer 2 16-Bit Mode Block Diagram
M
T
H
3
M
T
3
L
CKCON
M
T
2
H
M
T
2
L
0
1
M
T
1
M
T
0
S
C
A
1
S
C
A
0
TR2
TCLK
Rev. 1.4
Overflow
TL2
TMR2RLL TMR2RLH
TMR2L
To SMBus
TMR2H
Reload
To ADC,
SMBus
T2SPLIT
TF2LEN
T2XCLK
T2SOF
TF2H
TF2L
C8051F320/1
TR2
Interrupt
217
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