C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 208
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C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Master Mode Timing* (See Figure 18.8 and Figure 18.9)
T
T
T
T
Slave Mode Timing* (See Figure 18.10 and Figure 18.11)
T
T
T
T
T
T
T
T
T
T
*Note: T
MCKH
MCKL
MIS
MIH
SE
SD
SEZ
SDZ
CKH
CKL
SIS
SIH
SOH
SLH
Parameter
SYSCLK
is equal to one period of the device system clock (SYSCLK).
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change (CKPHA = 1
ONLY)
Table 18.1. SPI Slave Timing Parameters
Description
Rev. 1.4
1 x T
1 x T
1 x T
2 x T
2 x T
5 x T
5 x T
2 x T
2 x T
6 x T
SYSCLK
Min
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
SYSCLK
0
+ 20
4 x T
4 x T
4 x T
8 x T
Max
—
—
—
—
—
—
—
—
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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