C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 198
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C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 198 of 250
- Download datasheet (2Mb)
C8051F320/1
18.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
198
Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection
Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram
Figure 18.2. Multiple-Master Mode Connection Diagram
Device 1
Master
Master
Device
Master
Device
GPIO
MISO
MOSI
GPIO
MISO
MOSI
MISO
MOSI
NSS
SCK
SCK
SCK
NSS
Diagram
Rev. 1.4
GPIO
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
NSS
Device 2
Master
Device
Device
Device
Slave
Slave
Slave
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