C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 48
C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bits7–0: ADC0 Data Word Low-Order Bits.
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bit2:
Bits1–0: UNUSED. Read = 00b; Write = don’t care.
Bits7–0: ADC0 Data Word High-Order Bits.
AD0SC4
R/W
Bit7
R/W
Bit7
R/W
Bit7
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always
read ‘0’.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.
AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
For AD0LJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1–0 are the upper 2 bits of the
10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word.
AD0SC
AD0SC3
R/W
R/W
Bit6
R/W
Bit6
Bit6
SFR Definition 5.4.
SFR Definition 5.3.
SFR Definition 5.5.
=
SYSCLK
--------------------- - 1
CLK
AD0SC2
R/W
R/W
Bit5
R/W
Bit5
Bit5
SAR
–
AD0SC1
R/W
Bit4
R/W
Bit4
R/W
Bit4
ADC0H: ADC0 Data Word MSB
ADC0CF: ADC0 Configuration
ADC0L: ADC0 Data Word LSB
Rev. 1.4
AD0SC0 AD0LJST
R/W
Bit3
R/W
Bit3
R/W
Bit3
R/W
Bit2
R/W
Bit2
R/W
Bit2
R/W
R/W
Bit1
R/W
Bit1
Bit1
-
R/W
R/W
Bit0
R/W
Bit0
Bit0
-
SFR Address:
SFR Address:
SFR Address:
00000000
Reset Value
Reset Value
00000000
11111000
Reset Value
0xBD
0xBC
0xBE
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