C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 59
C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPTnCN (shown
in Figure 7.1 and Figure 7.4). The amount of negative hysteresis voltage is determined by the settings of
the CPnHYN bits. As shown in Figure 7.3, settings of 20, 10 or 5 mV of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “9.3. Interrupt Handler” on page 87.) The CPnFIF flag is set to
‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.
(Programmed with CP0HYP Bits)
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CP0-
CP0+
VIN+
VIN-
Disabled
V
OL
Figure 7.3. Comparator Hysteresis Plot
V
OH
+
_
CP0
Positive Hysteresis
Maximum
OUT
Rev. 1.4
Negative Hysteresis
Disabled
Negative Hysteresis
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
C8051F320/1
59
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