C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 152
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C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F320/1
15.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in Figure 15.11 through
Figure 15.13. The associated interrupt enable bits are located in the USB registers shown in Figure 15.14
through Figure 15.16. A USB0 interrupt is generated when any of the USB interrupt flags is set to ‘1’. The
USB0 interrupt is enabled via the EIE1 SFR (see Section “9.3. Interrupt Handler” on page 87).
Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’.
152
Bits7-0:
Bits7-3:
Bits2-0:
Bit7
Bit7
R
R
-
USB Register Definition 15.10. FRAMEH: USB0 Frame Number High
USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low
Frame Number Low
This register contains bits7-0 of the last received frame number.
Unused. Read = 0. Write = don’t care.
Frame Number High Byte
This register contains bits10-8 of the last received frame number.
Bit6
Bit6
R
R
-
Bit5
Bit5
R
R
-
Frame Number Low
Bit4
Bit4
R
R
-
Rev. 1.4
Bit3
Bit3
R
R
-
Bit2
Bit2
R
R
Frame Number High
Bit1
Bit1
R
R
Bit0
Bit0
R
R
USB Address:
USB Address:
00000000
00000000
Reset Value
Reset Value
0x0D
0x0C
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