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ATMEGA328P-AU
ATMEGA328P-AU | |
---|---|
Manufacturer Part Number | ATMEGA328P-AU |
Description | MCU AVR 32K FLASH 32TQFP |
Manufacturer | Atmel |
Series | AVR® ATmega |
ATMEGA328P-AU datasheets |
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Specifications of ATMEGA328P-AU | |||
---|---|---|---|
Core Processor | AVR | Core Size | 8-Bit |
Speed | 20MHz | Connectivity | I²C, SPI, UART/USART |
Peripherals | Brown-out Detect/Reset, POR, PWM, WDT | Number Of I /o | 23 |
Program Memory Size | 32KB (16K x 16) | Program Memory Type | FLASH |
Eeprom Size | 1K x 8 | Ram Size | 2K x 8 |
Voltage - Supply (vcc/vdd) | 1.8 V ~ 5.5 V | Data Converters | A/D 8x10b |
Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
Package / Case | 32-TQFP, 32-VQFP | Processor Series | ATMEGA32x |
Core | AVR8 | Data Bus Width | 8 bit |
Data Ram Size | 2 KB | Interface Type | 2-Wire, SPI, USART |
Maximum Clock Frequency | 20 MHz | Number Of Programmable I/os | 23 |
Number Of Timers | 3 | Maximum Operating Temperature | + 85 C |
Mounting Style | SMD/SMT | 3rd Party Development Tools | EWAVR, EWAVR-BL |
Development Tools By Supplier | ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT | Minimum Operating Temperature | - 40 C |
On-chip Adc | 10 bit, 8 Channel | Cpu Family | ATmega |
Device Core | AVR | Device Core Size | 8b |
Frequency (max) | 20MHz | Total Internal Ram Size | 2KB |
# I/os (max) | 23 | Number Of Timers - General Purpose | 3 |
Operating Supply Voltage (typ) | 2.5/3.3/5V | Operating Supply Voltage (max) | 5.5V |
Operating Supply Voltage (min) | 1.8V | Instruction Set Architecture | RISC |
Operating Temp Range | -40C to 85C | Operating Temperature Classification | Industrial |
Mounting | Surface Mount | Pin Count | 32 |
Package Type | TQFP | Controller Family/series | AVR MEGA |
No. Of I/o's | 23 | Eeprom Memory Size | 1KB |
Ram Memory Size | 2KB | Cpu Speed | 20MHz |
Rohs Compliant | Yes | For Use With | ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Other names | ATMEGA328P-20AU ATMEGA328P-20AU Q3790246 |
ATMEGA48A-PU PDF datasheetATMEGA48A-PU PDF datasheet #2ATMEGA48PA-MMH PDF datasheet #3ATMEGA328P-AU PDF datasheet #4
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ATmega48A/48PA/88A/88PA/168A/168PA/328/328
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
15-10
and
Table 15-5.
CS12
0
0
0
0
1
1
1
1
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
15.11.3
TCCR1C – Timer/Counter1 Control Register C
Bit
(0x82)
Read/Write
Initial Value
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on
the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0
bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the
value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always
read as zero.
8271C–AVR–08/10
Figure
15-11.
Clock Select Bit Description
CS11
CS10
Description
0
0
No clock source (Timer/Counter stopped).
0
1
clk
/1 (No prescaling)
I/O
1
0
clk
/8 (From prescaler)
I/O
1
1
clk
/64 (From prescaler)
I/O
0
0
clk
/256 (From prescaler)
I/O
0
1
clk
/1024 (From prescaler)
I/O
1
0
External clock source on T1 pin. Clock on falling edge.
1
1
External clock source on T1 pin. Clock on rising edge.
7
6
5
FOC1A
FOC1B
–
R/W
R/W
R
R
0
0
0
4
3
2
1
–
–
–
–
R
R
R
0
0
0
0
Figure
0
–
TCCR1C
R
0
138
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