MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part NumberATMEGA328P-AU
DescriptionMCU AVR 32K FLASH 32TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA328P-AU datasheets
 

Specifications of ATMEGA328P-AU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size32KB (16K x 16)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-TQFP, 32-VQFPProcessor SeriesATMEGA32x
CoreAVR8Data Bus Width8 bit
Data Ram Size2 KBInterface Type2-Wire, SPI, USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os23
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 8 ChannelCpu FamilyATmega
Device CoreAVRDevice Core Size8b
Frequency (max)20MHzTotal Internal Ram Size2KB
# I/os (max)23Number Of Timers - General Purpose3
Operating Supply Voltage (typ)2.5/3.3/5VOperating Supply Voltage (max)5.5V
Operating Supply Voltage (min)1.8VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count32
Package TypeTQFPController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size1KB
Ram Memory Size2KBCpu Speed20MHz
Rohs CompliantYesFor Use WithATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246
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ATmega48A/48PA/88A/88PA/168A/168PA/328/328
23.9.3
ADCL and ADCH – The ADC Data Register
23.9.3.1
ADLAR = 0
Bit
(0x79)
(0x78)
Read/Write
Initial Value
23.9.3.2
ADLAR = 1
Bit
(0x79)
(0x78)
Read/Write
Initial Value
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
262.
23.9.4
ADCSRB – ADC Control and Status Register B
Bit
(0x7B)
Read/Write
Initial Value
• Bit 7, 5:3 – Reserved
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
8271C–AVR–08/10
15
14
13
12
ADC7
ADC6
ADC5
ADC4
7
6
5
4
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
15
14
13
12
ADC9
ADC8
ADC7
ADC6
ADC1
ADC0
7
6
5
4
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
ACME
R
R/W
R
R
0
0
0
0
11
10
9
8
ADC9
ADC8
ADC3
ADC2
ADC1
ADC0
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
11
10
9
8
ADC5
ADC4
ADC3
ADC2
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
”ADC Conversion Result” on
3
2
1
0
ADTS2
ADTS1
ADTS0
R
R/W
R/W
R/W
0
0
0
0
ADCH
ADCL
ADCH
ADCL
ADCSRB
266