MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part NumberATMEGA328P-AU
DescriptionMCU AVR 32K FLASH 32TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA328P-AU datasheets
 


Specifications of ATMEGA328P-AU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size32KB (16K x 16)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-TQFP, 32-VQFPProcessor SeriesATMEGA32x
CoreAVR8Data Bus Width8 bit
Data Ram Size2 KBInterface Type2-Wire, SPI, USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os23
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 8 ChannelCpu FamilyATmega
Device CoreAVRDevice Core Size8b
Frequency (max)20MHzTotal Internal Ram Size2KB
# I/os (max)23Number Of Timers - General Purpose3
Operating Supply Voltage (typ)2.5/3.3/5VOperating Supply Voltage (max)5.5V
Operating Supply Voltage (min)1.8VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count32
Package TypeTQFPController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size1KB
Ram Memory Size2KBCpu Speed20MHz
Rohs CompliantYesFor Use WithATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246
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ATmega48A/48PA/88A/88PA/168A/168PA/328/328
27.8.1
Serial Programming Pin Mapping
Table 27-17. Pin Mapping Serial Programming
Symbol
27.8.2
Serial Programming Algorithm
When writing serial data to the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, data is
clocked on the rising edge of SCK.
When reading data from the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, data is
clocked on the falling edge of SCK. See
To program and verify the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P in the serial
programming mode, the following sequence is recommended (See Serial Programming Instruc-
tion set in
1. Power-up sequence:
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of
the address. If polling (RDY/BSY) is not used, the user must wait at least t
issuing the next page (See
before the Flash write operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY) is not used, the
user must wait at least t
chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 6 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is
8271C–AVR–08/10
Pins
MOSI
PB3
MISO
PB4
SCK
PB5
Figure 27-9
Table 27-19 on page
313):
and GND while RESET and SCK are set to “0”. In some sys-
CC
Table
27-18). Accessing the serial programming interface
before issuing the next byte (See
WD_EEPROM
I/O
Description
I
Serial Data in
O
Serial Data out
I
Serial Clock
for timing details.
WD_FLASH
Table
27-18). In a
before
312