MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part NumberATMEGA328P-AU
DescriptionMCU AVR 32K FLASH 32TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA328P-AU datasheets
 


Specifications of ATMEGA328P-AU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size32KB (16K x 16)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-TQFP, 32-VQFPProcessor SeriesATMEGA32x
CoreAVR8Data Bus Width8 bit
Data Ram Size2 KBInterface Type2-Wire, SPI, USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os23
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 8 ChannelCpu FamilyATmega
Device CoreAVRDevice Core Size8b
Frequency (max)20MHzTotal Internal Ram Size2KB
# I/os (max)23Number Of Timers - General Purpose3
Operating Supply Voltage (typ)2.5/3.3/5VOperating Supply Voltage (max)5.5V
Operating Supply Voltage (min)1.8VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count32
Package TypeTQFPController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size1KB
Ram Memory Size2KBCpu Speed20MHz
Rohs CompliantYesFor Use WithATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246
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ATmega48A/48PA/88A/88PA/168A/168PA/328/328
7.5.1
General Purpose I/O Registers
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P contains three General Purpose I/O
Registers. These registers can be used for storing any information, and they are particularly use-
ful for storing global variables and Status Flags. General Purpose I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC
instructions.
7.6
Register Description
7.6.1
EEARH and EEARL – The EEPROM Address Register
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
• Bits 15:9] – Reserved
These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will
always read as zero.
• Bits 8:0 – EEAR[8:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
256/512/512/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 255/511/511/1023. The initial value of EEAR is undefined. A proper value must
be written before the EEPROM may be accessed.
EEAR8 is an unused bit in ATmega 48A/48PA and must always be written to zero.
7.6.2
EEDR – The EEPROM Data Register
Bit
0x20 (0x40)
Read/Write
Initial Value
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
7.6.3
EECR – The EEPROM Control Register
Bit
0x1F (0x3F)
Read/Write
Initial Value
• Bits 7:6 – Reserved
These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will
always read as zero.
8271C–AVR–08/10
15
14
13
12
EEAR7
EEAR6
EEAR5
EEAR4
7
6
5
4
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
X
X
X
X
7
6
5
4
MSB
R/W
R/W
R/W
R/W
0
0
0
0
7
6
5
4
EEPM1
EEPM0
R
R
R/W
R/W
0
0
X
X
11
10
9
8
EEAR8
EEAR3
EEAR2
EEAR1
EEAR0
3
2
1
0
R
R
R
R/W
R/W
R/W
R/W
R/W
0
0
0
X
X
X
X
X
3
2
1
0
LSB
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
EERIE
EEMPE
EEPE
EERE
R/W
R/W
R/W
R/W
0
0
X
0
EEARH
EEARL
EEDR
EECR
21