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ATMEGA328P-AU
ATMEGA328P-AU | |
|---|---|
| Manufacturer Part Number | ATMEGA328P-AU |
| Description | MCU AVR 32K FLASH 32TQFP |
| Manufacturer | Atmel |
| Series | AVR® ATmega |
| ATMEGA328P-AU datasheets |
|
Specifications of ATMEGA328P-AU | |||
|---|---|---|---|
| Core Processor | AVR | Core Size | 8-Bit |
| Speed | 20MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | Brown-out Detect/Reset, POR, PWM, WDT | Number Of I /o | 23 |
| Program Memory Size | 32KB (16K x 16) | Program Memory Type | FLASH |
| Eeprom Size | 1K x 8 | Ram Size | 2K x 8 |
| Voltage - Supply (vcc/vdd) | 1.8 V ~ 5.5 V | Data Converters | A/D 8x10b |
| Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 32-TQFP, 32-VQFP | Processor Series | ATMEGA32x |
| Core | AVR8 | Data Bus Width | 8 bit |
| Data Ram Size | 2 KB | Interface Type | 2-Wire, SPI, USART |
| Maximum Clock Frequency | 20 MHz | Number Of Programmable I/os | 23 |
| Number Of Timers | 3 | Maximum Operating Temperature | + 85 C |
| Mounting Style | SMD/SMT | 3rd Party Development Tools | EWAVR, EWAVR-BL |
| Development Tools By Supplier | ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT | Minimum Operating Temperature | - 40 C |
| On-chip Adc | 10 bit, 8 Channel | Cpu Family | ATmega |
| Device Core | AVR | Device Core Size | 8b |
| Frequency (max) | 20MHz | Total Internal Ram Size | 2KB |
| # I/os (max) | 23 | Number Of Timers - General Purpose | 3 |
| Operating Supply Voltage (typ) | 2.5/3.3/5V | Operating Supply Voltage (max) | 5.5V |
| Operating Supply Voltage (min) | 1.8V | Instruction Set Architecture | RISC |
| Operating Temp Range | -40C to 85C | Operating Temperature Classification | Industrial |
| Mounting | Surface Mount | Pin Count | 32 |
| Package Type | TQFP | Controller Family/series | AVR MEGA |
| No. Of I/o's | 23 | Eeprom Memory Size | 1KB |
| Ram Memory Size | 2KB | Cpu Speed | 20MHz |
| Rohs Compliant | Yes | For Use With | ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Other names | ATMEGA328P-20AU ATMEGA328P-20AU Q3790246 |
ATMEGA48A-PU PDF datasheetATMEGA48A-PU PDF datasheet #2ATMEGA48PA-MMH PDF datasheet #3ATMEGA328P-AU PDF datasheet #4
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PrevNext
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 19-8.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 19-9.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 19-10. UCSZn Bits Settings
UCSZn2
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
8271C–AVR–08/10
UPMn Bits Settings
UPMn1
UPMn0
0
0
0
1
1
0
1
1
USBS Bit Settings
USBSn
0
1
UCSZn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Stop Bit(s)
1-bit
2-bit
UCSZn0
Character Size
0
5-bit
1
6-bit
0
7-bit
1
8-bit
0
Reserved
1
Reserved
0
Reserved
1
9-bit
203
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