MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part NumberATMEGA328P-AU
DescriptionMCU AVR 32K FLASH 32TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA328P-AU datasheets
 


Specifications of ATMEGA328P-AU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size32KB (16K x 16)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-TQFP, 32-VQFPProcessor SeriesATMEGA32x
CoreAVR8Data Bus Width8 bit
Data Ram Size2 KBInterface Type2-Wire, SPI, USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os23
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 8 ChannelCpu FamilyATmega
Device CoreAVRDevice Core Size8b
Frequency (max)20MHzTotal Internal Ram Size2KB
# I/os (max)23Number Of Timers - General Purpose3
Operating Supply Voltage (typ)2.5/3.3/5VOperating Supply Voltage (max)5.5V
Operating Supply Voltage (min)1.8VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count32
Package TypeTQFPController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size1KB
Ram Memory Size2KBCpu Speed20MHz
Rohs CompliantYesFor Use WithATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246
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ATMEGA48A-PU PDF datasheetATMEGA48A-PU PDF datasheet #2ATMEGA48PA-MMH PDF datasheet #3ATMEGA328P-AU PDF datasheet #4
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Page 61/566

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ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Table 11-3.
BOOTRST
Note:
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega88A/88PA is:
Address Labels Code
0x000
0x001
0x002
0x003
0x004
0x005
0x006
0x007
0X008
0x009
0x00A
0x00B
0x00C
0x00D
0x00E
0x00F
0x010
0x011
0x012
0x013
0x014
0x015
0x016
0x017
0x018
0x019
;
0x01ARESET:
0x01B
0x01C
0x01D
0x01E
0x01F
8271C–AVR–08/10
Reset and Interrupt Vectors Placement in ATmega88A and ATmega88PA
IVSEL
Reset Address
1
0
0x000
1
1
0x000
0
0
Boot Reset Address
0
1
Boot Reset Address
1. The Boot Reset Address is shown in
means unprogrammed while “0” means programmed.
rjmp
RESET
rjmp
EXT_INT0
rjmp
EXT_INT1
rjmp
PCINT0
rjmp
PCINT1
rjmp
PCINT2
rjmp
WDT
rjmp
TIM2_COMPA
rjmp
TIM2_COMPB
rjmp
TIM2_OVF
rjmp
TIM1_CAPT
rjmp
TIM1_COMPA
rjmp
TIM1_COMPB
rjmp
TIM1_OVF
rjmp
TIM0_COMPA
rjmp
TIM0_COMPB
rjmp
TIM0_OVF
rjmp
SPI_STC
rjmp
USART_RXC
rjmp
USART_UDRE
rjmp
USART_TXC
rjmp
ADC
rjmp
EE_RDY
rjmp
ANA_COMP
rjmp
TWI
rjmp
SPM_RDY
ldi
r16, high(RAMEND); Main program start
out
SPH,r16
ldi
r16, low(RAMEND)
out
SPL,r16
sei
<instr>
xxx
Interrupt Vectors Start Address
0x001
Boot Reset Address + 0x001
0x001
Boot Reset Address + 0x001
Table 26-7 on page
291. For the BOOTRST Fuse “1”
Comments
; Reset Handler
; IRQ0 Handler
; IRQ1 Handler
; PCINT0 Handler
; PCINT1 Handler
; PCINT2 Handler
; Watchdog Timer Handler
; Timer2 Compare A Handler
; Timer2 Compare B Handler
; Timer2 Overflow Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; USART, RX Complete Handler
; USART, UDR Empty Handler
; USART, TX Complete Handler
; ADC Conversion Complete Handler
; EEPROM Ready Handler
; Analog Comparator Handler
; 2-wire Serial Interface Handler
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
(1)
61

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