MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part NumberATMEGA328P-AU
DescriptionMCU AVR 32K FLASH 32TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA328P-AU datasheets
 

Specifications of ATMEGA328P-AU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size32KB (16K x 16)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-TQFP, 32-VQFPProcessor SeriesATMEGA32x
CoreAVR8Data Bus Width8 bit
Data Ram Size2 KBInterface Type2-Wire, SPI, USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os23
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 8 ChannelCpu FamilyATmega
Device CoreAVRDevice Core Size8b
Frequency (max)20MHzTotal Internal Ram Size2KB
# I/os (max)23Number Of Timers - General Purpose3
Operating Supply Voltage (typ)2.5/3.3/5VOperating Supply Voltage (max)5.5V
Operating Supply Voltage (min)1.8VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count32
Package TypeTQFPController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size1KB
Ram Memory Size2KBCpu Speed20MHz
Rohs CompliantYesFor Use WithATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246
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Page 64/566

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ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Table 11-5 on page 64
tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations. This
is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in
the Boot section or vice versa.
Table 11-5.
BOOTRST
Note:
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega168A/168PA is:
Address Labels Code
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
0x001A
0x001C
0x001E
0x0020
0x0022
0x0024
0x0026
0x0028
0x002A
0x002C
0x002E
0x0030
0x0032
;
0x0033RESET:
8271C–AVR–08/10
shows reset and Interrupt Vectors placement for the various combina-
Reset and Interrupt Vectors Placement in ATmega168A and ATmega168PA
IVSEL
Reset Address
1
0
0x000
1
1
0x000
0
0
Boot Reset Address
0
1
Boot Reset Address
1. The Boot Reset Address is shown in
means unprogrammed while “0” means programmed.
jmp
RESET
jmp
EXT_INT0
jmp
EXT_INT1
jmp
PCINT0
jmp
PCINT1
jmp
PCINT2
jmp
WDT
jmp
TIM2_COMPA
jmp
TIM2_COMPB
jmp
TIM2_OVF
jmp
TIM1_CAPT
jmp
TIM1_COMPA
jmp
TIM1_COMPB
jmp
TIM1_OVF
jmp
TIM0_COMPA
jmp
TIM0_COMPB
jmp
TIM0_OVF
jmp
SPI_STC
jmp
USART_RXC
jmp
USART_UDRE
jmp
USART_TXC
jmp
ADC
jmp
EE_RDY
jmp
ANA_COMP
jmp
TWI
jmp
SPM_RDY
ldi
r16, high(RAMEND); Main program start
Interrupt Vectors Start Address
0x002
Boot Reset Address + 0x0002
0x002
Boot Reset Address + 0x0002
Table 26-7 on page
291. For the BOOTRST Fuse “1”
Comments
; Reset Handler
; IRQ0 Handler
; IRQ1 Handler
; PCINT0 Handler
; PCINT1 Handler
; PCINT2 Handler
; Watchdog Timer Handler
; Timer2 Compare A Handler
; Timer2 Compare B Handler
; Timer2 Overflow Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; USART, RX Complete Handler
; USART, UDR Empty Handler
; USART, TX Complete Handler
; ADC Conversion Complete Handler
; EEPROM Ready Handler
; Analog Comparator Handler
; 2-wire Serial Interface Handler
; Store Program Memory Ready Handler
(1)
64