LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 103

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
5. Memory Accelerator Module operating modes
UM10237_4
User manual
4.2 Instruction latches and data latches
4.3 Flash programming Issues
Code and Data accesses are treated separately by the Memory Accelerator Module.
There is a 128 bit Latch, a 15 bit Address Latch, and a 15 bit comparator associated with
each buffer (prefetch, branch trail, and data). Each 128 bit latch holds 4 words (4 ARM
instructions, or 8 Thumb instructions).
Also associated with each buffer are 32 4:1 Multiplexers that select the requested word
from the 128 bit line.
Since the Flash memory does not allow accesses during programming and erase
operations, it is necessary for the MAM to force the CPU to wait if a memory access to a
Flash address is requested while the Flash module is busy. (This is accomplished by
asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay
could result in a Watchdog time-out. The user will need to be aware of this possibility and
take steps to ensure that an unwanted Watchdog reset does not cause a system failure
while programming or erasing the Flash memory.
In order to preclude the possibility of stale data being read from the Flash memory, the
LPC2400 MAM holding latches are automatically invalidated at the beginning of any Flash
programming or erase operation. Any subsequent read from a Flash address will cause a
new fetch to be initiated after the Flash operation has completed.
Three modes of operation are defined for the MAM, trading off performance for ease of
predictability:
Fig 20. Simplified block diagram of the Memory Accelerator Module
Mode 0: MAM off. All memory requests result in a Flash read operation (see note 2
below). There are no instruction prefetches.
ARM LOCAL BUS
Rev. 04 — 26 August 2009
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
INTERFACE
BUS
MEMORY ADDRESS
FLASH MEMORY BANK
BUFFERS
UM10237
© NXP B.V. 2009. All rights reserved.
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