LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 74

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
8. Reset
9. Pin description
UM10237_4
User manual
The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip
power is applied, and when a brown-out condition is detected (see the System Control
Block chapter for details of Brown-Out Detect). The other reset is from the external Reset
pin and the Watchdog Timer.
A configuration bit in the SCS register, called EMC_Reset_Disable, allows control of how
the EMC is reset. The default configuration (EMC_Reset_Disable = 0) is that both EMC
resets are asserted when any type of reset event occurs. In this mode, all registers and
functions of the EMC are initialized upon any reset condition.
If EMC_Reset_Disable is set to 1, many portions of the EMC are only reset by a power-on
or brown-out event, in order to allow the EMC to retain its state through a warm reset
(external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be
maintained through a warm reset.
Table 5–66
Table 66.
Name
A[23:0]
D[31:0]
OE
BLS[3:0]
WE
CS[3:0]
DYCS[3:0]
CAS
RAS
Pad interface and control signal descriptions
shows the interface and control signal pins for the EMC.
Output 0x0000 0000
Output 0xF
Output 0xF
Type
Output
Output 1
Output 1
Output 0xF
Output 1
Output 1
Input/
Rev. 04 — 26 August 2009
Value on POR
reset
Data outputs =
0x0000 0000
Chapter 5: LPC24XX External Memory Controller (EMC)
Value during
self-refresh
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
0xF
1
1
Description
External memory address output.
Used for both static and SDRAM
devices. SDRAM memories use only
bits [14:0].
External memory data lines. These
are inputs when data is read from
external memory and outputs when
data is written to external memory.
Low active output enable for static
memory devices.
Low active byte lane selects. Used
for static memory devices.
Low active write enable. Used for
SDRAM and static memories.
Static memory chip selects. Default
active LOW. Used for static memory
devices.
SDRAM chip selects. Used for
SDRAM devices.
Column address strobe. Used for
SDRAM devices.
Row address strobe. Used for
SDRAM devices.
UM10237
© NXP B.V. 2009. All rights reserved.
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