LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 234

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
7.2.14 Transmit Status Vector 1 Register (TSV1 - 0xFFE0 015C)
7.2.15 Receive Status Vector Register (RSV - 0xFFE0 0160)
Table 218. Transmit Status Vector 0 register (TSV0 - address 0xFFE0 0158) bit description
[1]
The Transmit Status Vector 1 register (TSV1) is a Read Only register with an address of
0xFFE0 015C. The transmit status vector registers store the most recent transmit status
returned by the MAC. Since the status vector consists of more than 4 bytes, status is
distributed over two registers TSV0 and TSV1. These registers are provided for debug
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are
TSV1 register.
Table 219. Transmit Status Vector 1 register (TSV1 - address 0xFFE0 015C) bit description
The Receive status vector register (RSV) is a Read Only register with an address of
0xFFE0 0160. The receive status vector register stores the most recent receive status
returned by the MAC. This register is provided for debug purposes, because the
communication between driver software and the Ethernet block takes place primarily
through the frame descriptors. The status register contents are valid as long as the
internal status of the MAC is valid and should typically only be read when the transmit and
receive processes are halted.
Bit
10
11
27:12
28
29
30
31
Bit
15:0
19:16
31:20
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the
status of the received frame.
Symbol
Giant
Underrun
Total bytes
Control frame
Pause
Backpressure
VLAN
Symbol
Transmit byte count
Transmit collision
count
-
Rev. 04 — 26 August 2009
The frame was a control frame.
Function
Byte count in frame was greater than can be represented
in the transmit byte count field in TSV1.
Host side caused buffer underrun.
The total number of bytes transferred including collided
attempts.
The frame was a control frame with a valid PAUSE
opcode.
Carrier-sense method backpressure was previously
applied.
Frame’s length/type field contained 0x8100 which is the
VLAN protocol identifier.
Function
The total number of bytes in the frame, not counting the
collided bytes.
Number of collisions the current packet incurred during
transmission attempts. The maximum number of collisions
(16) cannot be represented.
Unused
halted.Table 11–219
Chapter 11: LPC24XX Ethernet
lists the bit definitions of the
UM10237
© NXP B.V. 2009. All rights reserved.
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0
0
Reset
value
0
0x0
0
0
0
Reset
value
0x0
0x0
0x0