LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 663

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
4. Register description
UM10237_4
User manual
4.1 Watchdog Mode Register (WDMOD - 0xE000 0000)
When the Watchdog counter underflows, the program counter will start from 0x0000 0000
as in the case of external reset. The Watchdog time-out flag (WDTOF) can be examined
to determine if the Watchdog has caused the reset condition. The WDTOF flag must be
cleared by software.
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
The Watchdog contains 4 registers as shown in
Table 584. Summary of Watchdog registers
[1]
The WDMOD register controls the operation of the Watchdog as per the combination of
WDEN and RESET bits.
Name
WDMOD
WDTC
WDFEED
WDTV
WDCLKSEL Watchdog clock source selection register.
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Description
Watchdog mode register. This register contains
the basic mode and status of the Watchdog
Timer.
Watchdog timer constant register. This register
determines the time-out value.
Watchdog feed sequence register. Writing 0xAA
followed by 0x55 to this register reloads the
Watchdog timer with the value contained in
WDTC.
Watchdog timer value register. This register
reads out the current value of the Watchdog
timer.
Rev. 04 — 26 August 2009
Chapter 27: LPC24XX WatchDog Timer (WDT)
Table 27–584
Access Reset
R/W
R/W
WO
RO
R/W
below.
Value
0
0xFF
NA
0xFF
0
UM10237
© NXP B.V. 2009. All rights reserved.
[1]
Address
0xE000 0000
0xE000 0004
0xE000 0008
0xE000 000C
0xE000 0010
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