MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 347

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 12
Ethernet Physical Transceiver (EPHYV2)
12.1
The Ethernet physical transceiver (EPHY) is an IEEE 802.3 compliant 10BASE-T/100BASE-TX Ethernet
PHY transceiver. The EPHY module supports both the medium-independent interface (MII) and the MII
management interface. The EPHY requires a 25-MHz crystal for its basic operation.
12.1.1
Freescale Semiconductor
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IEEE 802.3 compliant
Full-/half-duplex support in all modes
Medium-independent interface (MII), which has these characteristics:
— Capable of supporting both 10 Mbps and 100 Mbps data rates
— Data and delimiters are synchronous to clock references
— Provides independent four-bit wide transmit and receive data paths
— Provides a simple management interface
Supports auto-negotiation
Auto-negotiation next page ability
Single RJ45 connection
1:1 common transformer
Baseline wander correction
Digital adaptive equalization
Integrated wave-shaping circuitry
Far-end fault detect
MDC rates up to 25 MHz
Supports MDIO preamble suppression
Jumbo packet
2.5 V CMOS
2.5 V MII interface
125 MHz clock generator and timing recovery
Loopback modes
Introduction
Features
MC9S12NE64 Data Sheet, Rev. 1.1
347