MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 349

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.2
This section contains the EPHY external pin descriptions.
12.2.1
Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
12.2.2
Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
12.2.3
Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
Freescale Semiconductor
RXN
RXP
TXP
TXN
RBIAS
100BASE-TX
LOOPBACK
External Signal Descriptions
PHY_TXP — EPHY Twisted Pair Output +
PHY_TXN — EPHY Twisted Pair Output –
PHY_RXP — EPHY Twisted Pair Input +
100BASE-TX
10BASE-T
RECEIVER
RECEIVER
100BASE-TX
VOLTAGE/ CURRENT
10BASE-T
DRIVER
DRIVER
REFERENCES
10BASE-T
DIG LOOP B
Figure 12-2. PHY Sub Block Diagram
POLARITY CORRECTION
(COARSE EQUALIZER)
DIGITAL EQUALIZER
MC9S12NE64 Data Sheet, Rev. 1.1
TIMING CONTROL
MLT-3 ENCODE
VGA CONTROL
BLW CONTROL
LINK DETECT
SCRAMBLER
SQUELCH
100BASE-TX
DIG LOOP B
SLICER
100BASE-TX
10BASE-T
PLL
PLL
NEGOTIATE
AUTO
MLT-3 DECODE
DESCRAMBLER
4B / 5B
ENCODE
MANCHESTER ENCODER
DIGITAL WAVE SHAPING
MANCHESTER DECODE
CLOCK RECOVERY
CARRIER SENSE
COLLISION
4B/5B
DECODE
External Signal Descriptions
CONFIGURATION
MANAGEMENT
REGISTERS
LOOPBACK
(MII)
MII
MII
CLOCK
MDIO
REF
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