MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 359

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.3.3.5 Auto-Negotiate (A/N) Advertisement Register
The auto-negotiation (A/N) process requires four registers to communicate link information with its link
partner: A/N advertisement register (MII register 4), A/N link partner ability register (MII register 5), A/N
expansion register (MII register 6), and the A/N next page transmit register (MII register 7).
Figure 12-10
register sets the selector field, bits 4.4:0, to 00001 to indicate that it is IEEE Standard 802.3 compliant. The
technology ability fields (4.9:5) are set according to the values in the MII status register (1.15:11). The MI
can set the technology ability field bits before renegotiations to allow management to auto-negotiate to an
alternate common mode.
MII Register Address 4 (%00100)
Read: Anytime
Write: Never
NXTP — Next Page
RFLT — Remote Fault
FLCTL — Flow Control
TAF100FD — 100BASE-TX Full-Duplex
TAF100HD — 100BASE-TX Half-Duplex
TAF10FD — 10BASE-T Full-Duplex
Freescale Semiconductor
RESET:
W
R
1 = Capable of sending next pages
0 = Not capable of sending next pages
1 = Remote fault
0 = No remote fault
1 = Advertise implementation of the optional MAC control sublayer and pause function as specified
0 = No MAC-based flow control
1 = 100BASE-TX full -duplex capable
0 = Not 100BASE-TX full-duplex capable
1 = 100BASE-TX half-duplex capable
0 = Not 100BASE-TX half-duplex capable
1 = 10BASE-T full-duplex capable
0 = Not 10BASE-T full-duplex capable
NXTP
15
in IEEE standard clause 31 and anex 31B of 802.3. Setting FLCTL has no effect except to set
the corresponding bit in the FLP stream
1
shows the contents of the A/N advertisement register. On power-up, before A/N starts, the
= Unimplemented or Reserved
14
0
0
RFLT
13
0
Figure 12-10. Auto Negotiate Advertisement Register
12
0
0
11
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
FLCTL
10
0
9
0
0
100FD
TAF
8
1
100HD
TAF
7
1
10FD
TAF
6
1
10HD
TAF
5
1
Memory Map and Register Descriptions
4
0
SELECTORFIELD[4:0]
3
0
2
0
1
0
0
1
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