D13003TF16V Renesas Electronics America, D13003TF16V Datasheet - Page 32

• Manufacturer Part Number: D13003TF16V
• Description: IC H8/3003 ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13003TF16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 1-3 Pin Functions (cont)
Type
System control RES
Interrupts
Address bus
Data bus
Bus control
Symbol
RESO
STBY
BREQ
BACK
NMI
IRQ
IRQ
A
D
CS
AS
RD
HWR
LWR
WAIT
23
15
7
7
0
to A
to D
to CS
to
0
0
0
Pin No.
QFP-112
71
19
70
67
68
72
18 to 17,
25 to 24,
103 to 101
98 to 95,
65 to 54,
52 to 45
43 to 36
34 to 27
16 to 13
101 to 104
77
78
79
80
66
I/O
Input
Output Reset output: Outputs a reset signal to
Input
Input
Output Bus request acknowledge: Indicates that the
Input
Input
Output Address bus: Outputs address signals
Input/
output
Output Chip select: Select signals for areas 7 to 0
Output Address strobe: Goes low to indicate valid
Output Read: Goes low to indicate reading from the
Output High write: Goes low to indicate writing to the
Output Low write: Goes low to indicate writing to the
Input
12
Name and Function
Reset input: When driven low, this pin resets
the H8/3003
external devices
Standby: When driven low, this pin forces
a transition to hardware standby mode
Bus request: Used by an external bus master
to request the bus right from the H8/3003
bus has been granted to an external bus
master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 7 to 0: Maskable interrupt
request pins
Data bus: Bidirectional data bus
address output on the address bus
external address space
external address space; indicates valid data on
the upper data bus (D
external address space; indicates valid data on
the lower data bus (D
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
7
15
to D
to D
0
).
8
).