D13003TF16V Renesas Electronics America, D13003TF16V Datasheet - Page 497

• Manufacturer Part Number: D13003TF16V
• Description: IC H8/3003 ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13003TF16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.4 SCI Interrupts
The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error
interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 13-12
lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled
by the TIE, TEIE, and RIE bits in SCR. Each interrupt request is sent separately to the interrupt
controller.
The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. The TEI interrupt is
requested when the TEND flag is set to 1 in SSR. The TXI interrupt request can activate the
DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. The
TEI interrupt request cannot activate the DMAC.
The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR. The RXI interrupt request can
activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF
flag to 0. The ERI interrupt request cannot activate the DMAC.
DMAC channels in group 0 can be activated by interrupts from SCI channel 0. DMAC channels in
group 1 can be activated by interrupts from SCI channel 1.
Table 13-12 SCI Interrupt Sources
Interrupt
ERI
RXI
TXI
TEI
Description
Receive error (ORER, FER, or PER)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
477
Priority
High
Low