D13003TF16V Renesas Electronics America, D13003TF16V Datasheet - Page 328

• Manufacturer Part Number: D13003TF16V
• Description: IC H8/3003 ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13003TF16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word or byte access.
Buffer registers are initialized to H'FFFF by a reset and in standby mode.
10.2.10 Timer Control Registers (TCR)
TCR is an 8-bit register. The ITU has five TCRs, one in each channel.
Channel
0
1
2
3
4
Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects
the edge or edges of external clock sources, and selects how the counter is cleared.
TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit
Initial value
Read/Write
Abbreviation
TCR0
TCR1
TCR2
TCR3
TCR4
Reserved bit
—
—
7
1
CCLR1
Counter clear 1/0
These bits select the counter clear source
R/W
Function
TCR controls the timer counter. The TCRs in all channels are
functionally identical. When phase counting mode is selected in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to
TPSC0 in TCR2 are ignored.
6
0
CCLR0
R/W
5
0
308
CKEG1
Clock edge 1/0
These bits select external clock edges
R/W
4
0
CKEG0
R/W
3
0
TPSC2
R/W
Timer prescaler 2 to 0
These bits select the
counter clock
2
0
TPSC1
R/W
1
0
TPSC0
R/W
0
0