Z8F0413HH005EG Zilog, Z8F0413HH005EG Datasheet - Page 109

• Manufacturer Part Number: Z8F0413HH005EG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4108; Z8F0413HH005EG

PS024314-0308
1
0
Idle State
of Line
Clear To Send (CTS) Operation
MULTIPROCESSOR (9-Bit) Mode
Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format
3. Clears the UART Receiver interrupt in the applicable Interrupt Request register.
4. Executes the
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow
control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is
sampled one system clock before beginning any new character transmission. To delay
transmission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character trans-
missions, this action is typically performed during Stop Bit transmission. If CTS deasserts
in the middle of a character transmission, the current character is sent completely.
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9
selective communication when a number of processors share a common UART bus. In
MULTIPROCESSOR mode (also referred to as 9-bit mode), the multiprocessor bit (
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as displayed in
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9
Multiprocessor control bit. The UART Control 1 and Status 1 registers provide
MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the UART Address Compare register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed
to it. The determination of whether a frame of data is addressed to the UART can be made
Start
more data.
Bit0
lsb
Bit1
IRET
Figure
Bit2
instruction to return from the interrupt-service routine and await
13. The character format is given below:
Bit3
Data Field
Bit4
Bit5
Universal Asynchronous Receiver/Transmitter
Bit6
Z8 Encore! XP
msb
Bit7
th
Product Specification
bit) becomes the
MP
®
th
F0823 Series
) bit for
1
Stop Bit(s)
2
MP
) is
99