Z8F0413HH005EG Zilog, Z8F0413HH005EG Datasheet - Page 57

• Manufacturer Part Number: Z8F0413HH005EG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4108; Z8F0413HH005EG

Table 23. Port A–C High Drive Enable Sub-Registers (PxHDE)
Table 24. Port A–C Stop Mode Recovery Source Enable Sub-Registers (PxSMRE)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
PSMRE7
PHDE7
R/W
R/W
If 04H in Port A–C Address Register, accessible through the Port A–C Control Register
If 05H in Port A–C Address Register, accessible through the Port A–C Control Register
7
0
7
0
0 = The drains are enabled for any output mode (unless overridden by the alternate
function).
1 = The drain of the associated pin is disabled (open-drain mode).
Port A–C High Drive Enable Sub-Registers
The Port A–C High Drive Enable sub-register
A–C Control register by writing
the Port A–C High Drive Enable sub-registers to 1 configures the specified port pins for
high current output drive operation. The Port A–C High Drive Enable sub-register affects
the pins directly and, as a result, alternate functions are also affected.
PHDE[7:0]—Port High Drive Enabled.
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–C Stop Mode Recovery Source Enable Sub-Registers
The Port A–C Stop Mode Recovery Source Enable sub-register
through the Port A–C Control register by writing
Setting the bits in the Port A–C Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
PSMRE6
PHDE6
R/W
R/W
6
0
6
0
PSMRE5
PHDE5
R/W
R/W
5
0
5
0
PSMRE4
PHDE4
04H
R/W
R/W
4
0
4
0
to the Port A–C Address register. Setting the bits in
PSMRE3
PHDE3
R/W
R/W
(Table
3
0
3
0
05H
23) is accessed through the Port
to the Port A–C Address register.
PSMRE2
Z8 Encore! XP
PHDE2
R/W
R/W
2
0
2
0
General-Purpose Input/Output
(Table
Product Specification
PSMRE1
PHDE1
R/W
R/W
24) is accessed
1
0
1
0
®
F0823 Series
PSMRE0
PHDE0
R/W
R/W
0
0
0
0
47