Z8F0413HH005EG Zilog, Z8F0413HH005EG Datasheet - Page 132

• Manufacturer Part Number: Z8F0413HH005EG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4108; Z8F0413HH005EG

Table 72. ADC Control Register 0 (ADCCTL0)
ADC Control Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
Note:
Caution:
ADC Control Register 0
CEN
R/W
ADC comp
7
0
Software Compensation Procedure
The value read from the ADC high and low byte registers are uncompensated. The user
mode software must apply gain and offset correction to this uncompensated value for
maximum accuracy. The following formula yields the compensated value:
where GAINCAL is the gain calibration byte, OFFCAL is the offset calibration byte and
ADC
two’s complement format, as are the compensated and uncompensated ADC values.
The offset compensation is performed first, followed by the gain compensation. One bit of
resolution is lost because of rounding on both the offset and gain computations. As a result
the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and
10 data bits. Also note that in the second term, the multiplication must be performed
before the division by 2
The following sections define the ADC control registers.
The ADC Control register selects the analog input channel and initiates the
analog-to-digital conversion.
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion is complete.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already
in progress, the conversion restarts. This bit remains 1 until the conversion is complete.
Although the ADC can be used without the gain and offset compensation, it does exhibit
non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC
range but requires the ADC results to be scaled by a factor of 8/7.
uncomp
REFSELL
R/W
=
6
0
is the uncompensated value read from the ADC. The OFFCAL value is in
(
ADC uncomp OFFCAL
REFEXT
R/W
16
5
0
. Otherwise, the second term evaluates to zero incorrectly.
–
CONT
R/W
4
0
F70H
)
+
(
(
ADC uncomp OFFCAL
R/W
3
0
Z8 Encore! XP
R/W
–
2
0
ANAIN[3:0]
Product Specification
Analog-to-Digital Converter
R/W
) ∗ GAINCAL
1
0
®
F0823 Series
R/W
) 2 16
0
0
⁄
122