Z8F0413HH005EG Zilog, Z8F0413HH005EG Datasheet - Page 38

• Manufacturer Part Number: Z8F0413HH005EG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4108; Z8F0413HH005EG

Table 12. Reset Status Register (RSTSTAT)
Reset Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
Reset or Stop Mode Recovery Event
Power-On Reset
Reset using RESET pin assertion
Reset using WDT time-out
Reset using the OCD (OCTCTL[1] set to 1)
Reset from STOP Mode using DBG Pin driven Low
Stop Mode Recovery using GPIO pin transition
Stop Mode Recovery using WDT time-out
Stop Mode Recovery Using the External RESET Pin
Reset Status Register
POR
R
7
When the Z8 Encore! XP F0823 Series device is in STOP mode and the external RESET
pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET
pin, the Low pulse must be greater than the minimum width specified, or it is ignored. For
more details, see
The Reset Status (RSTSTAT) register is a read-only register that indicates the source of
the most recent Reset event, indicates a Stop Mode Recovery event, and indicates a
Watchdog Timer time-out. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer control register, which is write-
only
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event is occurred. This bit is reset to 0 if a WDT
time-out or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is
read.
See descriptions below
(Table
STOP
R
6
12).
Electrical Characteristics
WDT
R
5
EXT
R
4
0
FF0H
POR
1
0
0
1
1
0
0
on page 193.
R
3
0
STOP
0
0
0
0
0
1
1
Z8 Encore! XP
WDT
R
2
0
0
0
1
0
0
0
1
Reset and Stop Mode Recovery
Reserved
Product Specification
EXT
0
1
0
0
0
0
0
R
1
0
®
F0823 Series
R
0
0
28