Z16F2811FI20SG Zilog, Z16F2811FI20SG Datasheet - Page 164

IC ZNEO MCU FLASH 128K 80QFP

Z16F2811FI20SG

Manufacturer Part Number
Z16F2811FI20SG
Description
IC ZNEO MCU FLASH 128K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheets

Specifications of Z16F2811FI20SG

Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4534

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16F2811FI20SG
Manufacturer:
Zilog
Quantity:
155
Part Number:
Z16F2811FI20SG
Manufacturer:
Zilog
Quantity:
10 000
PS022008-0810
interrupt, however the receive data register must be read to clear the OE bit. In this case
software must write
Break state.
LIN-UART Data and Error Handling Procedure
Figure 28
service routines.
Baud Rate Generator Interrupts
If the BRGCTL bit of the
with MSEL = 000b)
UART receiver interrupt asserts when the LIN-UART baud rate generator reloads. This
Figure 28. LIN-UART Receiver Interrupt Service Routine Flow
displays the recommended procedure for use in LIN-UART receiver interrupt
Read Data
10b
register is set, and the
to the
Multiprocessor Control Register (LIN-UART Control 1 Register
P R E L I M I N A R Y
No
LinState
clears RDA bit and
Read Data which
resets error bits
Discard Data
Read Status
Receiver
Receiver
Interrupt
Ready
Errors?
field, forcing the LIN slave back to Wait for
REN
Yes
bit of the Control0 register is 0, the LIN-
Product Specification
ZNEO
Z16F Series
LIN-UART
148

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