Z16F2811FI20SG Zilog, Z16F2811FI20SG Datasheet - Page 166

• Manufacturer Part Number: Z16F2811FI20SG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4534

Noise Filter
PS022008-0810
System
Clock
Architecture
LIN-UART
When configured as a general purpose timer, the BRG interrupt interval is calculated using
the following equation:
A noise filter circuit is included, which filters noise on a digital input signal such as UART
receive data before the data is sampled by the block. This is a requirement for protocols
with a noisy environment.
The noise filter includes following features:
•
•
•
•
•
Figure 29
network.
UART BRG Interrupt Interval (s)
Noise filter enable (
Provides an active low saturated state output (
Synchronizes the receive input data to the system clock.
Noise filter control (
The digital filter output has hysteresis.
or included (
counter digital filter. The available widths range is from 4 to11 bits.
noise.
displays how the noise filter is integrated with the LIN-UART for use on a LIN
NFEN, NFCTL
NFEN
FiltSatB
RxD
TxD
NFEN)
= 1) in the receive data path.
NFCTL[2:0])
P R E L I M I N A R Y
input selects whether the noise filter is bypassed (
Noise Filter
input selects the width of the up/down saturating
=
System Clock Period (s) BRG[15:0]
FiltSatB
), used to indicate presence of
TxD
RxD
Product Specification
ZNEO
RxD
TxD
Transceiver

Z16F Series
LIN
NFEN
LIN-UART
= 0)
150