Z16F2811FI20SG Zilog, Z16F2811FI20SG Datasheet - Page 228

• Manufacturer Part Number: Z16F2811FI20SG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4534

PS022008-0810
S
Note:
Slave Address
Figure 44. Data Transfer Format - Master Write Transaction with 10-Bit Address
1st Byte
15. When there is no more data to be sent, software responds by setting the STOP bit of
16. If no additional transaction is queued by the Master, software clears the
17. The I
18. The I
If the Slave terminates the transaction early by responding with a Not Acknowledge
during the transfer, the I
terminate the transaction by setting either the STOP bit (end transaction) or the START bit
(end this transaction, start a new one). In this case, it is not necessary for software to set
the FLUSH bit of the I2CCTL register to flush the data that was previously written but not
transmitted. The I
Acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 44
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 
7-bit addressing.
The procedure for a Master transmit operation to a 10-bit addressed Slave is given below:
1. Software initializes the MODE field in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE interrupt by writing the first Slave address byte
5. Software asserts the
6. The I
the I
I
with 7- or 10-bit addressing (I
The MODE field selects the address width for this node when addressed as a Slave,
not for the remote Slave. Software asserts the IEN bit in the I
(11110xx0). The least-significant bit must be 0 for the write operation.
2
C Control register.
2
2
2
2
2
C Control register (or START bit to initiate a new transaction).
displays the data transfer format from a Master to a 10-bit addressed Slave.
C Controller completes transmission of the data on the SDA signal.
C Controller sends the STOP condition to the I
C interrupt asserts because the I
C Controller sends the START condition to the I
W=0
2
C Controller hardware automatically flushes transmit data in this Not
A
2
START
C Controller asserts the
Slave Address
P R E L I M I N A R Y
2nd Byte
bit of the I
2
C bus protocol allows mixing Slave address types).
2
C Control register to enable Transmit interrupts.
2
2
A
C Data register is empty.
C Control register.
2
Data
C Mode register for Master/Slave mode
NCKI
11110XX
interrupt and halts. Software must
2
A
C bus.
2
C Slave.
. The two bits
I
2
C Master/Slave Controller
Product Specification
Data
2
C Control register.
ZNEO
XX
A/A
TXI
Z16F Series
are the two
bit of the
F/S
212