Z16F2811FI20SG Zilog, Z16F2811FI20SG Datasheet - Page 201

• Manufacturer Part Number: Z16F2811FI20SG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4534

PS022008-0810
SCK (SSMD = 010,
MOSI, MISO
(SSPO = 0)
CLKPOL = 0)
PHASE = 0,
SPI Protocol Configuration
SS
register just prior to or in synchronous with the first data byte of the frame being written.
Note that the number of bits per frame is a value other than an integral number of 8-bits by
setting NUMBITS to a value other than 0.
Example
To send 20 bits/frame, set NUMBITS = 5 and read/write 4 bytes per frame. The transmit
data must be left justified and the receive data must be right justified.
The transaction is terminated when the master has no more data to transmit. After the last
bit is transferred, SCLK stops and SS and SSV returns to their default states. If TEOF is
not set on the last byte, a transmit underrun error occurs at this point.
This section describes in detail how to configure the ESPI block for the SPI protocol. In
the SPI protocol the master sources the SCK and asserts slave select signals to one or more
slaves. The slave select signals are typically active Low.
SPI Master Operation
The ESPI block is configured for MASTER mode operation by setting the
the ESPICTL register. The SSMD field of the ESPI Mode register is set to 000 for SPI
protocol mode. The
NUMBITS field in the ESPI mode register must be consistent with the Slave SPI devices.
Typically for an SPI master
Figure 38. I2S mode (SSMD = 010)
SSV=1
Phase
Bit7
frame n
(may be multiple
bytes)
P R E L I M I N A R Y
,
SSIO = 1
Clkpol
, and
Bit0
and
Wor
SSPO = 0
SSV=0
Bit7
bits in the ESPICTL register and the
frame n + 1
. The appropriate GPIO pins are
Enhanced Serial Peripheral Interface
Bit0
Product Specification
ZNEO
Bit 7
MMEN
Z16F Series
bit =
1
in
185