Z16F2811FI20SG Zilog, Z16F2811FI20SG Datasheet - Page 211

• Manufacturer Part Number: Z16F2811FI20SG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4534

Table 101. ESPI Mode Register (ESPIMODE)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
ESPI Mode Register
7
MMEN—ESPI Master Mode Enable
This bit controls the data I/O pin selection and SCK direction.
0 = Data-out on MISO, data-in on MOSI (used in SPI Slave mode), SCK is an input.
1 = Data-out on MOSI, data-in on MISO (used in SPI Master mode), SCK is an output.
The ESPI Mode register (see
the ESPI IO pins.
SSMD—SLAVE SELECT Mode
This field selects the behavior of SS as a framing signal. For a detailed description of these
modes, see
000 = SPI mode
When SSIO = 1, the SS pin is driven directly from the SSV bit in the Transmit Data
Command register. The Master software or DMA must set SSV (or a GPIO output if the
SS pin is not connected to the appropriate Slave) to the asserted state prior to or on the
same clock cycle with which the transmit data register is written with the initial byte. 
At the end of a frame (after the last RDRF event), SSV is deasserted by software.
Alternatively, SSV is automatically deasserted by hardware if the TEOF bit in the
Transmit Data Command register is set when the last transmit byte is loaded. In SPI mode,
SCK is active only for data transfer (one clock cycle per bit transferred).
001 = LOOPBACK Mode
When ESPI is configured as Master (MMEN = 1) the outputs are deasserted and data is
looped from shift register out to shift register in. When ESPI is configured as a Slave
(MMEN = 0) and SS in asserts, MISO (Slave output) is tied to MOSI (Slave input) to
provide an a remote loop back (echo) function.
010 = I2S Mode
In this mode, the value from SSV will be output by the Master on the SS pin one SCK
period before the data and will remain in that state until the start of the next frame.
Typically this mode is used to send back-to-back frames with SS alternating on each
frame. A frame boundary is indicated in the Master when SSV changes. A frame boundary
SSMD
R/W
000
6
Slave Select
5
on page 177.
P R E L I M I N A R Y
Table
4
101) configures the character bit width and mode of
FF_E263H
NUMBITS[2:0]
R/W
000
3
Enhanced Serial Peripheral Interface
2
Product Specification
ZNEO
SSIO
R/W
1
0
Z16F Series
SSPO
R/W
0
0
195