DSPIC33FJ12GP202-I/SS Microchip Technology, DSPIC33FJ12GP202-I/SS Datasheet
DSPIC33FJ12GP202-I/SS
Specifications of DSPIC33FJ12GP202-I/SS
Related parts for DSPIC33FJ12GP202-I/SS
DSPIC33FJ12GP202-I/SS Summary of contents
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... Microchip Technology Inc. dsPIC33FJ12GP201/202 High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70264D ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Four processor exceptions On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • ...
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... Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/SSOP/QFN Note: See Table 1 for the exact peripheral features per device. Preliminary © 2009 Microchip Technology Inc. ...
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... TABLE 1: dsPIC33FJ12GP201/202 CONTROLLER FAMILIES Device dsPIC33FJ12GP201 18 12 dsPIC33FJ12GP202 28 12 Note 1: Only two out of three timers are remappable. 2: Only two out of three interrupts are remappable. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 ...
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... CAP DDCORE 10 Vss 19 (1) /CN1/RB4 TDO/SDA1/RP9 11 18 TCK/SCL1/RP8 INT0/RP7 DD 16 (1) /CN27/RB5 ASCL1/RP6 14 15 Preliminary = Pins are tolerant /CN11/RB15 /CN12/RB14 (1) /CN21/RB9 /CN22/RB8 /CN23/RB7 = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 (1) /CN24/RB6 © 2009 Microchip Technology Inc. ...
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... Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 AN8/RP13 21 AN9/RP12 TMS/RP11 dsPIC33FJ12GP202 4 18 TDI/RP10 CAP DDCORE TDO/SDA1/RP9 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70264D-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... Figure 1-1 shows a general block diagram of the core and peripheral modules dsPIC33FJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 the latest in the Preliminary DS70264D-page 7 ...
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... Address Address Loop Latch Latch Control Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ UART1 ADC1 PWM1-2 CNx I2C1 SPI1 Preliminary PORTA PORTB 16 Remappable Pins © 2009 Microchip Technology Inc. ...
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... No Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for analog modules. This pin must be connected at all times. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...
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... REF reference for ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
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... REAL ICE™ In-Circuit Debugger User's Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “ ...
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... DS70264D-page 14 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternately, connect 10k resistor to V unused pins and drive the output to logic low. Preliminary © 2009 Microchip Technology Inc ...
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... MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts ...
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... Data Latch Data Latch PCL X RAM Y RAM Address Address Loop Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2009 Microchip Technology Inc. ...
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... AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 ...
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... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70264D-page 18 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 (2) Preliminary ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70264D-page 20 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...
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... The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 3.6 DSP Engine The DSP engine consists of a high-speed 17-bit x ...
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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70264D-page 22 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2009 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input ...
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... Section 3.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary © 2009 Microchip Technology Inc. to data saturation (see ...
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... The MSb of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 3.6.3 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70264D-page 26 Preliminary © 2009 Microchip Technology Inc. ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY FOR dsPIC33FJ12GP201/202 DEVICES © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 4.1 Program Address Space The program dsPIC33FJ12GP201/202 devices is 4M instructions ...
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... EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2009 Microchip Technology Inc. ...
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... Alternately, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 4.2.3 SFR SPACE The first 2 Kbytes of the near data space, from 0x0000 to 0x07FF, is primarily occupied by Special Function ® ...
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... Optionally Mapped into Program Memory 0xFFFF DS70264D-page 30 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0x0BFE 0x0C00 0x1FFFF 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2009 Microchip Technology Inc. ...
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... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class). © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 ...
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TABLE 4-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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TABLE 4-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
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TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-17: PORTB REGISTER MAP FOR dsPIC33FJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 TRISB13 ...
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TABLE 4-20: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
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... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary © 2009 Microchip Technology Inc. addressing modes are ...
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... Not all instructions support all the address- ing modes given above. Individual instruc- tions may support different subsets of these addressing modes. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
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... MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary the difference between the © 2009 Microchip Technology Inc. ...
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... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 4.5.1 BIT-REVERSED ADDRESSING ...
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... TABLE 4-23: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70264D-page 46 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word, Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal © 2009 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70264D-page 48 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2009 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2009 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ instructions (192 bytes sin- gle program memory word, and erase program mem- source ...
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... Refer to Section 5.3 “Programming Operations” for further details. Preliminary stalls (waits) until the PROGRAMMING TIME T )% × FRC Accuracy FRC Tuning 11064 Cycles = × × 0.05 1 0.00375 – 11064 Cycles = × × 0.05 – 1 0.00375 – © 2009 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 (1) U-0 U-0 — — ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70264D-page 54 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2009 Microchip Technology Inc. ...
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... DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state, and some are unaffected. ...
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... SWDTEN bit setting. DS70264D-page 58 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 (1) (CONTINUED) ...
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... Preliminary ) after a PWRT ensures that the system PWRT for more has FSCM Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2009 Microchip Technology Inc. ...
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... T BOR extension BOR time T Programmable 0-128 ms nominal PWRT power-up time delay 900 μs maximum T Fail-safe Clock FSCM Monitor Delay © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Vbor V BOR T BOR 3 T PWRT T OSCD Reset Time has elapsed. POR ensures the voltage regulator output becomes stable. ...
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... Reset delay (T rises above the V ) for proper BOR BOR PWRT BOR PWRT BOR PWRT Preliminary ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT DD trip point. BOR V BOR V BOR V BOR © 2009 Microchip Technology Inc. ...
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... Watchdog Reset. Refer to “Watchdog Timer (WDT)” for more information on Watchdog Reset. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 6.7 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive ...
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... MCLR Reset RESET instruction WDT Time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR © 2009 Microchip Technology Inc. ...
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... The dsPIC33FJ12GP201/202 devices implement unique interrupts and four nonmaskable traps. These are summarized in Table 7-1 and Table 7-2. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1 ...
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... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70264D-page 66 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC33FJ12GP201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2009 Microchip Technology Inc. ...
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... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt ...
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... R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...
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... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 R/W-0 COVAERR COVBERR ...
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... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70264D-page 72 Preliminary © 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — ...
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... Interrupt request has not occurred DS70264D-page 74 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary DS70264D-page 75 ...
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... Interrupt request has not occurred DS70264D-page 76 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request not enabled DS70264D-page 78 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary DS70264D-page 79 ...
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... Interrupt request not enabled DS70264D-page 80 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70264D-page 82 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 85
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
Page 86
... Interrupt is priority 1 000 = Interrupt source is disabled DS70264D-page 84 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 87
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
Page 88
... Interrupt is priority 1 000 = Interrupt source is disabled DS70264D-page 86 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 89
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...
Page 90
... Unimplemented: Read as ‘0’ DS70264D-page 88 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
Page 92
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70264D-page 90 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 93
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 94
... NOTES: DS70264D-page 92 Preliminary © 2009 Microchip Technology Inc. ...
Page 95
... SOSCI Note 1: See Figure 8-2 for PLL details the Oscillator is used with modes, an external parallel resistor with the value of 1 MΩ must be connected. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • ...
Page 96
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by Equation 8-2. OSC Preliminary © 2009 Microchip Technology Inc. Configuration bits, is divided OSC ) and the ...
Page 97
... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 EQUATION 8-3: F ------------- 0.8-8.0 MHz ...
Page 98
... PLL modes. DS70264D-page 96 (1) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary © 2009 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 99
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 (1) ...
Page 100
... Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70264D-page 98 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 101
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...
Page 102
... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. DS70264D-page 100 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 103
... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 When the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits ...
Page 104
... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. DS70264D-page 102 Preliminary © 2009 Microchip Technology Inc. ...
Page 105
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ12GP201/202 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 106
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible ® DSC © 2009 Microchip Technology Inc. ...
Page 107
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 U-0 ...
Page 108
... DS70264D-page 106 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown ...
Page 109
... CK WR Port Data Latch Read LAT Read Port © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as source ...
Page 110
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary devices to © 2009 Microchip Technology Inc. ...
Page 111
... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 112
... OC1 Output Enable OC2 Output Enable Default U1TX Output U1RTS Output 4 OC1 Output OC2 Output Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> Output Enable RPn Output Data 18 19 © 2009 Microchip Technology Inc. ...
Page 113
... IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 RPn tied to default port pin 00000 RPn tied to UART1 Transmit ...
Page 114
... Unimplemented: Read as ‘0’ DS70264D-page 112 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary R/W-1 R/W-1 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 115
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R< ...
Page 116
... Input tied to RP1 00000 = Input tied to RP0 DS70264D-page 114 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 117
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R< ...
Page 118
... Input tied to RP1 00000 = Input tied to RP0 DS70264D-page 116 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR< ...
Page 120
... Input tied to RP1 00000 = Input tied to RP0 DS70264D-page 118 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 121
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R< ...
Page 122
... Input tied to RP0 DS70264D-page 120 U-0 U-0 — — R/W-1 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 ...
Page 124
... Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 125
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 ...
Page 126
... Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the source ...
Page 128
... Unimplemented: Read as ‘0’ DS70264D-page 126 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an generated with the Timer3 interrupt flags. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 12.1 32-bit Operation To configure the Timer2/3 feature for 32-bit operation: 1. Set the corresponding T32 control bit. ...
Page 130
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70264D-page 128 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...
Page 131
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70264D-page 129 ...
Page 132
... Unimplemented: Read as ‘0’ DS70264D-page 130 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 133
... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits have no effect. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 (1) — ...
Page 134
... NOTES: DS70264D-page 132 Preliminary © 2009 Microchip Technology Inc. ...
Page 135
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 • Capture timer value on every edge (rising and falling) • Prescaler Capture Event modes: ...
Page 136
... Input capture module turned off DS70264D-page 134 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 137
... OUTPUT COMPARE MODULE BLOCK DIAGRAM OCxRS OCxR Comparator OCTSEL TMR3 TMR2 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 The Output Compare module has multiple operating modes: • Active-Low One-Shot mode • Active-High One-Shot mode • Toggle mode source. To • Delayed One-Shot mode • Continuous Pulse mode • ...
Page 138
... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary — © 2009 Microchip Technology Inc. ...
Page 139
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — ...
Page 140
... NOTES: DS70264D-page 138 Preliminary © 2009 Microchip Technology Inc. ...
Page 141
... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Each SPI module consists of a 16-bit shift register, SPIxSR (where 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates status conditions ...
Page 142
... DS70264D-page 140 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 143
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 ...
Page 144
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS70264D-page 142 (3) (3) Preliminary © 2009 Microchip Technology Inc. ...
Page 145
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — ...
Page 146
... NOTES: DS70264D-page 144 Preliminary © 2009 Microchip Technology Inc. ...
Page 147
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 16.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing ...
Page 148
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...
Page 149
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 150
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70264D-page 148 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master master) Preliminary © 2009 Microchip Technology Inc. ...
Page 151
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 R/C-0 HS — ...
Page 152
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70264D-page 150 2 C slave device address byte. Preliminary © 2009 Microchip Technology Inc. ...
Page 153
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — ...
Page 154
... NOTES: DS70264D-page 152 Preliminary © 2009 Microchip Technology Inc. ...
Page 155
... FIGURE 17-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 • Baud rates ranging from 4 Mbps to 61 bps at 4x mode at 40 MIPS • 4-deep First-In First-Out (FIFO) Transmit Data Buffer • ...
Page 156
... DS70264D-page 154 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 157
... Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 MODE REGISTER (CONTINUED) ...
Page 158
... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 159
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 STATUS AND CONTROL REGISTER (CONTINUED) x ...
Page 160
... NOTES: DS70264D-page 158 Preliminary © 2009 Microchip Technology Inc. ...
Page 161
... There is only one sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Depending on the particular device pinout, the ADC can have analog input pins, designated AN0 through AN9. In addition, there are two analog input pins for external voltage reference connections ...
Page 162
... REF REF 2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation. DS70264D-page 160 Preliminary (1) ( REF DD REF SS ADC1BUF0 ADC1BUF1 ADC1BUF2 V V REFH REFL SAR ADC ADC1BUFE ADC1BUFF © 2009 Microchip Technology Inc. ...
Page 163
... FIGURE 18-2: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ12GP202 DEVICES AN0 AN9 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V - REF CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 AN9 V - REF CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 AN7 V - REF CH123NA CH123NB AN2 AN5 ...
Page 164
... T OSC 2: See the ADC Electrical Characteristics for the exact RC clock value. DS70264D-page 162 AD1CON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 when the PLL is enabled. If the PLL is not used, F OSC = 1/F . OSC Preliminary AD1CON3<15> equal OSC © 2009 Microchip Technology Inc. ...
Page 165
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 — ...
Page 166
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software is not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. DS70264D-page 164 Preliminary © 2009 Microchip Technology Inc. ...
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... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 — ...
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... Note 1: This bit only used if AD1CON1<SSRC> This bit is not used if AD1CON3<ADRC> DS70264D-page 166 R/W-0 R/W-0 R/W-0 (1) SAMC<4:0> R/W-0 R/W-0 R/W-0 (2) ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ( Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
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... Reserved 00 = Reserved If AD12B = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is not connected 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
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... Reserved 00 = Reserved If AD12B = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is not connected 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
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... Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 dsPIC33FJ12GP202 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 © ...
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... Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 dsPIC33FJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
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... Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 dsPIC33FJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 © ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1,2) R/W-0 R/W-0 CSS9 CSS8 bit 8 R/W-0 R/W-0 CSS1 CSS0 bit Bit is unknown . REFL (1,2,3) R/W-0 R/W-0 PCFG9 PCFG8 bit 8 R/W-0 R/W-0 PCFG1 PCFG0 bit Bit is unknown SS © 2009 Microchip Technology Inc. ...
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... FUID2 0xF80016 FUID3 Note 1: These reserved bits read as ‘1’ and must be programmed as ‘1’. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 19.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000 ...
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... Allow multiple reconfigurations OSC2 Pin Function bit (except in XT and HS modes OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled Crystal Oscillator mode Crystal Oscillator mode (External Clock) mode Preliminary © 2009 Microchip Technology Inc. ...
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... FPWRT<2:0> FPOR JTAGEN FICD ICS<1:0> FICD © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect Watchdog Timer enabled/disabled by user software (LPRC can be ...
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... The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to oper- ate while in Sleep or Idle modes and resets the device should V fall below the BOR threshold voltage. DD (1) . Preliminary . The main purpose of the BOR module © 2009 Microchip Technology Inc. ...
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... CLRWDT Instruction SWDTEN FWDTEN LPRC Clock (divide by N1) WINDIS © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 19.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed ...
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... BS = 256 IW 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h GS = 3584 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 768 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 3072 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 1792 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 2048 IW 001FFEh © 2009 Microchip Technology Inc. ...
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... The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
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... Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the dsPIC30F/33F Programmer’s Reference Manual (DS70157). Description Preliminary © 2009 Microchip Technology Inc. ...
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... Y data space prefetch address register for DSP instructions ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4...W7} Wyd © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Preliminary DS70264D-page 181 ...
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... Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Preliminary © 2009 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z ...
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... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...
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... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) Prefetch and store accumulator Preliminary © 2009 Microchip Technology Inc Status Flags Words Cycles Affected 1 18 N,Z,C,OV ...
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... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) ...
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... Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary © 2009 Microchip Technology Inc Status Flags Words Cycles Affected N,Z ...
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... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 21.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2009 Microchip Technology Inc. ...
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... REAL ICE offers significant advantages over competi- tive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 21.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
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... IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary © 2009 Microchip Technology Inc. ® L security ICs, CAN ® ...
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... Maximum allowable current is a function of device maximum power dissipation (see Table 22-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the V and PGEDx pins, which are able to sink/source 12 mA. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 SS .................................................................................. -0.3V to +5.6V SS ...
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... Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +140 °C -40 — +125 ° INT – T )/θ Typ Max Unit Notes 45 — °C — °C — °C — °C — °C — °C/W 1 © 2009 Microchip Technology Inc. ...
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... This is the limit to which These parameters are characterized by similarity, but are not tested in manufacturing voltage must remain at Vss for a minimum of 200 µs to ensure POR. DD © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3 ...
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... OSC1 DD Preliminary (3) 3.3V 10 MIPS (3) 3.3V 16 MIPS (3) 3.3V 20 MIPS (3) 3.3V 30 MIPS 3.3V 40 MIPS . SS © 2009 Microchip Technology Inc. ...
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... Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled These parameters are characterized, but are not tested in manufacturing. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 198
... Preliminary ) PD Conditions (3,4) Base Power-Down Current (3,5) Watchdog Timer Current: ΔI WDT -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS © 2009 Microchip Technology Inc. ...
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... Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for a list of 5V tolerant pins. © 2009 Microchip Technology Inc. dsPIC33FJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... DD core voltage DD Preliminary ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 2mA 3. 2mA 3. -2 -1 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions 2.55 V © 2009 Microchip Technology Inc. ...