DSPIC33FJ12GP202-I/SS Microchip Technology, DSPIC33FJ12GP202-I/SS Datasheet - Page 26

• Manufacturer Part Number: DSPIC33FJ12GP202-I/SS
• Description: IC DSPIC MCU/DSP 12K 28SSOP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12GP202-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SSOP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ12GP201/202
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow, and therefore, indicate that a
catastrophic overflow has occurred. If the COVTE bit in
the INTCON1 register is set, the SA and SB bits will
generate an arithmetic warning trap when saturation is
disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programs can check one bit in the
STATUS register to determine whether either accumu-
lator has overflowed, or one bit to determine whether
either accumulator has saturated. This is useful for
complex number arithmetic, which typically uses both
accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
• Bit 31 Overflow and Saturation:
• Bit 39 Catastrophic Overflow:
3.6.2.2
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator which is not targeted by the instruc-
DS70264D-page 24
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
value (0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator.
The SA or SB bit is set and remains set until
cleared by the user application. This condition is
referred to as ‘super saturation’ and provides pro-
tection against erroneous data or unexpected algo-
rithm problems (such as gain calculations).
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
Accumulator ‘Write Back’
Preliminary
tion into data space memory. The write is performed
across the X bus into combined X and Y address
space. The following addressing modes are supported:
• W13, Register Direct:
• [W13] + = 2, Register Indirect with Post-Increment:
3.6.2.3
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15
data value that is passed to the data space write satu-
ration logic. If rounding is not indicated by the instruc-
tion, a truncated 1.15 data value is stored and the least
significant word (lsw) is simply discarded.
Conventional rounding will zero-extend bit 15 of the
accumulator and will add it to the ACCxH word (bits 16
through 31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the accu-
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
A consequence of this algorithm is that over a succes-
sion of random rounding operations, the value tends to
be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the LSb (bit 16 of
the accumulator) of ACCxH is examined.
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified. Assuming that
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the
Section 3.6.2.4 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator
write-back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
mulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
is left unchanged.
bit 16 is effectively random in nature, this scheme
removes any rounding bias that may accumulate.
X
bus,
Round Logic
subject
© 2009 Microchip Technology Inc.
to
data
saturation
(see