DSPIC33FJ12GP202-I/SS Microchip Technology, DSPIC33FJ12GP202-I/SS Datasheet - Page 53

IC DSPIC MCU/DSP 12K 28SSOP

DSPIC33FJ12GP202-I/SS

Manufacturer Part Number
DSPIC33FJ12GP202-I/SS
Description
IC DSPIC MCU/DSP 12K 28SSOP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ12GP202-I/SS

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Package
28SSOP
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
5.0
The dsPIC33FJ12GP201/202 devices contain internal
Flash program memory for storing and executing appli-
cation code. The memory is readable, writable, and
erasable during normal operation over the entire V
range.
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJ12GP201/202 device to be
serially programmed while in the end application circuit.
This is done with two lines for programming clock and
programming data (one of the alternate programming
pin pairs: PGECx/PGEDx), and three other lines for
power (V
This allows users to manufacture boards with
unprogrammed devices and then program the digital
signal controller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
FIGURE 5-1:
© 2009 Microchip Technology Inc.
Note:
programming capability
FLASH PROGRAM MEMORY
DD
), ground (V
This data sheet summarizes the features
of the dsPIC33FJ12GP201/202 family of
devices. It is not intended to be a
comprehensive
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, Section 5. “Flash
Programming” (DS70191), which is
available from the Microchip web site
(www.microchip.com).
Using
Program Counter
Using
Table Instruction
User/Configuration
Space Select
ADDRESSING FOR TABLE REGISTERS
SS
) and Master Clear (MCLR).
reference
1/0
0
source.
TBLPAG Reg
8 bits
Preliminary
To
DD
Program Counter
dsPIC33FJ12GP201/202
24-bit EA
24 bits
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or ‘rows’ of 64 instructions (192 bytes) or a sin-
gle program memory word, and erase program mem-
ory in blocks or ‘pages’ of 512 instructions (1536
bytes).
5.1
Regardless of the method used, all programming of
Flash memory is done with the table-read and table-
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits <15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
Working Reg EA
16 bits
Table Instructions and Flash
Programming
0
Byte
Select
DS70264D-page 51

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