PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet
PIC18F458T-I/PT
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PIC18F458T-I/PT Summary of contents
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... Enhanced Flash Microcontrollers © 2006 Microchip Technology Inc. PIC18FXX8 Data Sheet 28/40-Pin High-Performance, with CAN Module DS41159E ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... SPI™ (Supports all 4 SPI modes C™ Master and Slave mode • Addressable USART module: - Supports interrupt-on-address bit © 2006 Microchip Technology Inc. PIC18FXX8 Advanced Analog Features: • 10-bit 8-channel Analog-to-Digital Converter module (A/D) with: - Conversion available during Sleep - channels available • ...
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... RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B 13 28 RD4/PSP4/ECCP1/P1A 14 27 RC7/RX/ RC6/TX/ RC5/SDO RC4/SDI/SDA RD3/PSP3/C2IN RD2/PSP2/C2IN PIC18F448 PIC18F458 MSSP Timers USART Master 8/16-bit SPI™ C™ 1 1/3 1 1/3 1 1 RB3/CANRX RB2/CANTX/INT2 RB1/INT1 RB0/INT0 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT © 2006 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) TQFP RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0 RB1/INT1 RB2/CANTX/INT2 RB3/CANRX SPDIP, SOIC MCLR/V RA0/AN0/CV RA1/AN1 RA2/AN2/V RA3/AN3/V RA4/T0CKI RA5/AN4/SS/LVDIN OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL © 2006 Microchip Technology Inc PIC18F448 PIC18F458 RB7/PGD RB6/PGC REF 3 26 RB5/PGM - REF ...
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... Appendix B: Device Differences......................................................................................................................................................... 385 Appendix C: Device Migrations .......................................................................................................................................................... 386 Appendix D: Migrating From Other PICmicro Index .................................................................................................................................................................................................. 387 On-Line Support................................................................................................................................................................................. 397 Systems Information and Upgrade Hot Line ...................................................................................................................................... 397 Reader Response .............................................................................................................................................................................. 398 PIC18FXX8 Product Identification System......................................................................................................................................... 399 DS41159E-page 4 ® Devices ..................................................................................................................... 386 © 2006 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. PIC18FXX8 DS41159E-page 5 ...
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... PIC18FXX8 NOTES: DS41159E-page 6 © 2006 Microchip Technology Inc. ...
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... Programmable Low-Voltage Detect Programmable Brown-out Reset CAN Module In-Circuit Serial Programming™ (ICSP™) Instruction Set 75 Instructions Packages © 2006 Microchip Technology Inc. 2. PIC18F2X8 devices implement 5 A/D channels, as opposed to 8 for PIC18F4X8 devices. 3. PIC18F2X8 devices implement 3 I/O ports, while PIC18F4X8 devices implement 5. 4. ...
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... ADC Synchronous USART Serial Port PORTA RA0/AN0/CV REF RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS/LVDIN OSC2/CLKO/RA6 PORTB RB0/INT0 RB1/INT1 RB2/CANTX/INT2 RB3/CANRX RB4 RB5/PGM RB6/PGC RB7/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 CAN Module © 2006 Microchip Technology Inc. ...
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... T1OSI T1OSO 4X PLL Precision Band Gap Reference Band Gap MCLR PBOR Timer0 Timer1 PLVD Data EEPROM Comparators CCP1 © 2006 Microchip Technology Inc. Data Bus<8> Data Latch 8 8 Data RAM up to 1536 Kbytes Address Latch PCLATH 12 Address<12> PCH PCL BSR Bank0, F ...
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... CLKI, OSC2/CLKO pins). Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin © 2006 Microchip Technology Inc. ...
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... AN3 V + REF RA4/T0CKI 6 RA4 T0CKI RA5/AN4/SS/LVDIN 7 RA5 AN4 SS LVDIN RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2006 Microchip Technology Inc. Pin Buffer PIC18F448/458 Type Type PDIP TQFP PLCC I/O TTL I Analog O Analog I/O ...
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... Receive signal for CAN bus. Digital I/O. Interrupt-on-change pin. Digital I/O. Interrupt-on-change pin. Low-voltage ICSP™ programming enable. Digital I/O. In-Circuit Debugger pin. Interrupt-on-change pin. ICSP programming clock. Digital I/O. In-Circuit Debugger pin. Interrupt-on-change pin. ICSP programming data © 2006 Microchip Technology Inc. ...
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... RC4/SDI/SDA 15 RC4 SDI SDA RC5/SDO 16 RC5 SDO RC6/TX/CK 17 RC6 TX CK RC7/RX/DT 18 RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2006 Microchip Technology Inc. Pin Buffer PIC18F448/458 Type Type PDIP TQFP PLCC I — I CMOS 17 ...
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... Parallel Slave Port data. ECCP1 capture/compare. ECCP1 PWM output A. Digital I/O. Parallel Slave Port data. ECCP1 PWM output B. Digital I/O. Parallel Slave Port data. ECCP1 PWM output C. Digital I/O. Parallel Slave Port data. ECCP1 PWM output © 2006 Microchip Technology Inc. ...
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... RD RE1/AN6/WR/C1OUT — RE1 AN6 WR C1OUT RE2/AN7/CS/C2OUT — RE2 AN7 CS C2OUT V 19 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2006 Microchip Technology Inc. Pin Buffer PIC18F448/458 Type Type PDIP TQFP PLCC I Analog I TTL I Analog I TTL ...
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... PIC18FXX8 NOTES: DS41159E-page 16 © 2006 Microchip Technology Inc. ...
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... Figure 2-4. The PIC18FXX8 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2006 Microchip Technology Inc. PIC18FXX8 FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OSC CONFIGURATION) ...
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... OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). ) and capacitor (C ) values and the EXT EXT RC OSCILLATOR MODE PIC18FXX8 Internal OSC1 Clock OSC2/CLKO /4 OSC 100 k EXT C > EXT © 2006 Microchip Technology Inc. ...
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... FIGURE 2-5: PLL BLOCK DIAGRAM OSC2 F Crystal F Osc OSC1 © 2006 Microchip Technology Inc. FIGURE 2-4: Clock from Ext. System 2.5 HS4 (PLL) A Phase Locked Loop circuit is provided as a program- mable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. ...
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... DD SS U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared T SCLK Clock Source U-0 U-0 R/W-1 — — SCS bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... T (drawing not to scale). OST OSC © 2006 Microchip Technology Inc. The sequence of events that takes place when switch- ing from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place ...
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... Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram indicat- ing the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes is shown in Figure 2-10 PLL T SCS T OSC OSC SCS © 2006 Microchip Technology Inc. ...
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... Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2006 Microchip Technology Inc. Reset until the device power supply and clock are stable. For additional information on Reset operation, see Section 3.0 “Reset”. ...
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... PIC18FXX8 NOTES: DS41159E-page 24 © 2006 Microchip Technology Inc. ...
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... Ripple Counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. © 2006 Microchip Technology Inc. PIC18FXX8 state on Power-on Reset, MCLR, WDT Reset, Brown- out Reset, MCLR Reset during Sleep and by the RESET instruction ...
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... Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above BV DD execute the additional time delay. to rise to an accept- DD falls below param- DD rises above while the Power- the Power-up Timer will DD © 2006 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (000008h or 000018h). © 2006 Microchip Technology Inc. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS41159E-page 28 T PWRT T OST T PWRT T OST T PWRT T OST © 2006 Microchip Technology Inc CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL © 2006 Microchip Technology Inc PWRT T OST T PWRT T OST T PLL ...
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... N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A © 2006 Microchip Technology Inc. Wake-up via WDT or Interrupt (3) ---0 uuuu (3) uuuu uuuu (3) uuuu uuuu (3) uu-u uuuu ---u uuuu uuuu uuuu ( --uu uuuu ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). © 2006 Microchip Technology Inc. MCLR Reset Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uu-- uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu 0000 0000 ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). © 2006 Microchip Technology Inc. MCLR Reset Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuu- uuuu uuuu uuuu ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). © 2006 Microchip Technology Inc. MCLR Reset Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuu- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- --uu uuuu uuuu uuuu uuuu ...
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... Read ‘0’ 1FFFFFh 200000h © 2006 Microchip Technology Inc. PIC18FXX8 Figure 4-1 shows the diagram for program memory map and stack for the PIC18F248 and PIC18F448. Figure 4-2 shows the diagram for the program memory map and stack for the PIC18F258 and PIC18F458. ...
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... POR occurs. Note: Returning a value of zero to the underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and stack appropriate actions can be taken. System for return stack © 2006 Microchip Technology Inc. ...
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... Value at POR FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS TOSU TOSH 00h 1Ah Note 1: No RAM associated with this address; always maintained ‘0’s. © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-0 — SP4 SP3 W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 4.8.1 “Computed GOTO”). © 2006 Microchip Technology Inc. ...
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... In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). © 2006 Microchip Technology Inc ...
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... Fetch 4 Opcode Memory 0E55h 55h 0Eh 0EF03h, 0F000h 03h 0EFh 00h 0F0h 0C123h, 0F456h 23h 0C1h 56h 0F4h Flush Fetch SUB_1 Execute SUB_1 Address 000007h 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h 000011h 000012h © 2006 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2006 Microchip Technology Inc. instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function. The offset value (value in WREG) specifies the number of bytes that the program counter should advance ...
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... The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as ‘0’s. See Table 4-1 for addresses for the SFRs. © 2006 Microchip Technology Inc. ...
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... Bank 1 FFh 00h = 0010 Bank 2 FFh = 0011 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh © 2006 Microchip Technology Inc. 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 300h Unused Read ‘00h’ EFFh F00h Unused ...
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... BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The next 160 bytes are Special Function Registers (from Bank 15). When the BSR is used to specify the RAM location that the instruction uses. © 2006 Microchip Technology Inc. ...
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... CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip header file requirement. 5: These registers are not implemented on the PIC18F248 and PIC18F258. © 2006 Microchip Technology Inc. Name Address Name ...
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... F11h RXF4SIDL F10h RXF4SIDH F0Fh RXF3EIDL (4) F0Eh RXF3EIDH F0Dh RXF3SIDL F0Ch RXF3SIDH F0Bh RXF2EIDL F0Ah RXF2EIDH F09h RXF2SIDL F08h RXF2SIDH F07h RXF1EIDL F06h RXF1EIDH F05h RXF1SIDL F04h RXF1SIDH F03h RXF0EIDL F02h RXF0EIDH F01h RXF0SIDL F00h RXF0SIDH © 2006 Microchip Technology Inc. ...
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... Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... WR RD xx-0 x000 32, 60, 67 RXB1IP RXB0IP 32, 90 1111 1111 RXB1IF RXB0IF 32, 84 0000 0000 RXB1IE RXB0IE 32, 87 0000 0000 (1) TMR3IP ECCP1IP 32, 89 -1-1 1111 (1) TMR3IF ECCP1IF 32, 83 -0-0 0000 (1) TMR3IE ECCP1IE 32, 86 -0-0 0000 © 2006 Microchip Technology Inc. ...
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... Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...
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... TXB1D01 TXB1D00 35, 208 xxxx xxxx DLC1 DLC0 35, 209 -x-- xxxx EID1 EID0 35, 208 xxxx xxxx EID9 EID8 35, 207 xxxx xxxx EID17 EID16 35, 207 xxx- x-xx SID4 SID3 35, 207 xxxx xxxx TXPRI1 TXPRI0 35, 206 0000 0000 © 2006 Microchip Technology Inc. ...
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... Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... Section 4.12 “Indirect Addressing, INDF and FSR Registers” provides a description of indirect address- ing, which allows linear addressing of the entire RAM space. (3) From Opcode 0 (3) 00h 01h 000h 100h (1) 0FFh 1FFh Bank 0 Bank 1 0Eh 0Fh 0E00h 0F00h 0EFFh 0FFFh Bank 14 Bank 15 © 2006 Microchip Technology Inc. ...
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... A read from INDF1 reads the data from the address indicated by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. © 2006 Microchip Technology Inc. PIC18FXX8 If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all ‘0’s are read (zero bit is set). Similarly, if ...
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... PIC18FXX8 FIGURE 4-8: INDIRECT ADDRESSING 11 FSRnH Location Select Note 1: For register file map detail, see Table 4-1. DS41159E-page 56 Indirect Addressing FSR Register FSRnL 0000h Data (1) Memory 0FFFh © 2006 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). ...
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... Power-on Resets may be detected. U-0 U-0 R/W-1 R/W — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to the specifications for exact limits. © 2006 Microchip Technology Inc. 5.1 EEADR Register The address register can address maximum of 256 bytes of data EEPROM. ...
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... R = Readable bit -n = Value at POR DS41159E-page 60 U-0 R/W-0 R/W-x — FREE WRERR W = Writable bit S = Settable bit ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Unimplemented bit, read as ‘0’ Bit is unknown © 2006 Microchip Technology Inc. ...
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... BSF INTCON, GIE . . . BCF EECON1, WREN © 2006 Microchip Technology Inc. 5.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADR register and the data writ- ten to the EEDATA register. Then, the sequence in Example 5-2 must be followed to initiate the write cycle. ...
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... Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts information (e.g., program © 2006 Microchip Technology Inc. ...
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... Legend unknown unchanged reserved unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. © 2006 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 ...
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... PIC18FXX8 NOTES: DS41159E-page 64 © 2006 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18FXX8 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... WR bit in software prevents the accidental or premature termination of a write operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be When set, cleared in software. Table Latch (8-bit) TABLAT © 2006 Microchip Technology Inc. ...
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... Initiates an EEPROM read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-x — FREE WRERR ...
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... Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write 8 7 TBLPTRH WRITE – TBLPTR<21:3> READ – TBLPTR<21:0> the Table Pointer, TBLPTR will determine which program TBLPTRL 0 © 2006 Microchip Technology Inc. ...
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... TBLRD*+ MOVF TABLAT, W MOVWF WORD_MSB © 2006 Microchip Technology Inc. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... FLASH program memory ; access FLASH program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write 0AAH ; start erase (CPU stall) ; NOP needed for proper code execution ; re-enable interrupts © 2006 Microchip Technology Inc. ...
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... FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register © 2006 Microchip Technology Inc. 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. ...
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... TBLWT holding register. ; loop until buffers are full © 2006 Microchip Technology Inc. ...
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... MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. © 2006 Microchip Technology Inc. PIC18FXX8 ; get low byte of buffer data ; present data to table latch ; write data, perform a short write ...
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... RBIF 0000 000x 0000 000u — — RD xx-0 x000 uu-0 u000 (1) -1-1 1111 -1-1 1111 (1) -0-0 0000 -0-0 0000 (1) -0-0 0000 -0-0 0000 © 2006 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2006 Microchip Technology Inc. PIC18FXX8 7.2 Operation Example 7-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
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... PRODL RES1 ; Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 ; Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2006 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2006 Microchip Technology Inc. PIC18FXX8 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ® ...
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... INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2006 Microchip Technology Inc. Wake- Sleep mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL GIE/GIEH ...
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... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... This feature allows software polling. DS41159E-page 80 R/W-1 U-0 U-0 R/W-1 — — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-0 U-0 — ...
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... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2006 Microchip Technology Inc. bit, GIE (INTCON R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... No TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-0 (1) — EEIF BCLIF ...
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... Legend Readable bit -n = Value at POR DS41159E-page 84 R/W-0 R/W-0 R/W-0 R/W-0 ERRIF TXB2IF TXB1IF TXB0IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 RXB1IF RXB0IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ADIE RCIE TXIE ...
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... Legend Readable bit -n = Value at POR DS41159E-page 86 U-0 R/W-0 R/W-0 (1) — EEIE BCLIE (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 (1) LVDIE TMR3IE ECCP1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 89
... Enables the Receive Buffer 1 interrupt 0 = Disables the Receive Buffer 1 interrupt bit 0 RXB0IE: Receive Buffer 0 Interrupt Enable bit 1 = Enables the Receive Buffer 0 interrupt 0 = Disables the Receive Buffer 0 interrupt Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W-1 ERRIE TXB2IE TXB1IE TXB0IE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 90
... Legend Readable bit -n = Value at POR DS41159E-page 88 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 91
... ECCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. U-0 R/W-1 R/W-1 (1) — EEIP BCLIP ...
Page 92
... Legend Readable bit -n = Value at POR DS41159E-page 90 R/W-1 R/W-1 R/W-1 R/W-1 ERRIP TXB2IP TXB1IP TXB0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 RXB1IP RXB0IP bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 93
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-3. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-3. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-1 R-1 — — RI ...
Page 94
... Example 8-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. 0000h) in the ; W_TEMP is in Low Access bank ; STATUS_TEMP located anywhere ; BSR located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2006 Microchip Technology Inc. ...
Page 95
... Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. © 2006 Microchip Technology Inc. PIC18FXX8 Read-modify-write operations on the LATA register read and write the latched output value for PORTA. ...
Page 96
... From OSC1 Data Latch EN . OSC and RA4/T0CKI PIN BLOCK DIAGRAM (1) I/O pin N Data Latch Schmitt Trigger CK Q Input Buffer TRIS Latch TTL Input Buffer only. SS Oscillator Circuit V DD OSC2/CLKO P (2) RA6 pin Schmitt Trigger Input Buffer © 2006 Microchip Technology Inc. ...
Page 97
... PORTA Data Direction Register ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2006 Microchip Technology Inc. Function Input/output, analog input or analog comparator voltage reference output. Input/output or analog input. Input/output, analog input ...
Page 98
... ICSP mode entry. 2: When using Low-Voltage ICSP Program- ming (LVP), the pull-up on RB5 becomes disabled. If TRISB bit 5 is cleared, thereby setting RB5 as an output, LATB bit 5 must also be cleared for proper operation. © 2006 Microchip Technology Inc. ...
Page 99
... Set RBIF Q D From other RB7:RB4 pins EN RBx/INTx Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). © 2006 Microchip Technology Inc. FIGURE 9- (2) RBPU Weak P Pull-up Data Bus (1) ...
Page 100
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS41159E-page and Data Latch TRIS Latch TTL Input Buffer Schmitt Trigger Buffer and RB2/CANTX/ (1) INT2 pin Schmitt Trigger Weak P Pull-up (1) I/O pin © 2006 Microchip Technology Inc. ...
Page 101
... PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTCON3 INT2IP INT1IP — Legend unknown unchanged. Shaded cells are not used by PORTB. © 2006 Microchip Technology Inc. Function Bit 4 Bit 3 Bit 2 Bit 1 RB4 RB3 RB2 RB1 INT0IE RBIE ...
Page 102
... Timer1 Oscillator for Timer1/Timer3 Yes Timer1 Oscillator for Timer1/Timer3 No — 2 Yes SPI™/I C™ Master Clock 2 Yes I C Data Out Yes SPI Data Out Yes USART Async Xmit, Sync Clock Yes USART Sync Data Out © 2006 Microchip Technology Inc. ...
Page 103
... RC5 LATC LATC Data Output Register TRISC PORTC Data Direction Register Legend unknown unchanged © 2006 Microchip Technology Inc. Function Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. Input/output port pin or Timer1 oscillator input. Input/output port pin or Capture 1 input/Compare 1 output/ PWM1 output. Input/output port pin or synchronous serial clock for SPI™ ...
Page 104
... N Q Vss Q Schmitt Trigger and INITIALIZING PORTD ; Initialize PORTD by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; comparator off ; Value used to ; initialize data ; direction ; Set RD3:RD0 as inputs ; RD5:RD4 as outputs ; RD7:RD6 as inputs DD RD0/PSP0/ (1) C1IN+ pin © 2006 Microchip Technology Inc. ...
Page 105
... TRISE IBF OBF IBOV PSPMODE Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by PORTD. © 2006 Microchip Technology Inc. Function (1) Input/output port pin, Parallel Slave Port bit 0 or C1IN+ comparator input. (1) Input/output port pin, Parallel Slave Port bit 1 or C1IN- comparator input ...
Page 106
... Initialize PORTE by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RE1:RE0 as inputs ; RE2 as an output ; (RE4=0 - PSPMODE Off) (1) TRIS OVERRIDE Override Peripheral Yes PSP Yes PSP Yes PSP © 2006 Microchip Technology Inc. ...
Page 107
... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 108
... Write PORTE Data Latch — — Read PORTE Data Latch/ Write PORTE Data Latch — PCFG3 PCFG2 PCFG1 Function Value on Value on Bit 0 all other POR, BOR Resets TRISE0 0000 -111 0000 -111 ---- -xxx ---- -uuu ---- -xxx ---- -uuu PCFG0 00-- 0000 00-- 0000 © 2006 Microchip Technology Inc. ...
Page 109
... Figure 10-2 and Figure 10-3, respectively. FIGURE 10-2: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD IBF OBF PSPIF © 2006 Microchip Technology Inc. FIGURE 10-1: Data Bus WR LATD or PSPMODE WR PORTD Data Latch Q RD PORTD RD LATD Set Interrupt Flag PSPIF (PIR1<7>) Note: ...
Page 110
... CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 Value on Value on Bit 0 all other POR, BOR Resets xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RE0 ---- -xxx ---- -000 ---- -xxx ---- -uuu 0000 -111 0000 -111 RBIF 0000 000x 0000 000u © 2006 Microchip Technology Inc. ...
Page 111
... Prescale value Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. Register 11-1 shows the Timer0 Control register (T0CON). Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 112
... T0PS2, T0PS1, T0PS0 and Sync with Internal TMR0L Clocks Delay) CY PSA and Data Bus 8 TMR0L Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> © 2006 Microchip Technology Inc. ...
Page 113
... Shaded cells are not used by Timer0. Note 1: Bit 6 of PORTA, LATA and TRISA is enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes disabled and reads as ‘0’. © 2006 Microchip Technology Inc. 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “ ...
Page 114
... PIC18FXX8 NOTES: DS41159E-page 112 © 2006 Microchip Technology Inc. ...
Page 115
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. Register 12-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module, as well as contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled/ disabled by setting/clearing control bit, TMR1ON (T1CON register) ...
Page 116
... Clock T1CKPS1:T1CKPS0 TMR1CS 8 Special Event Trigger TMR1 TMR1L TMR1ON On/Off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized 0 Clock Input 1 Synchronize det 2 Sleep Input Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Sleep Input © 2006 Microchip Technology Inc. ...
Page 117
... Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR registers). This interrupt can be enabled/disabled by setting/clearing TMR1 Interrupt Enable bit, TMR1IE (PIE registers). © 2006 Microchip Technology Inc. 12.4 Resetting Timer1 Using a CCP Trigger Output If the CCP module is configured in Compare mode ...
Page 118
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu © 2006 Microchip Technology Inc. ...
Page 119
... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 120
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 © 2006 Microchip Technology Inc. ...
Page 121
... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP1 and ECCP1 clock source. ...
Page 122
... Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Trigger T3CCPx TMR3 CLR TMR3L TMR3ON On/Off OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Synchronized Clock Input Synchronize det 2 Sleep Input Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 Sleep Input © 2006 Microchip Technology Inc. ...
Page 123
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CON RD16 T3ECCP1 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2006 Microchip Technology Inc. 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to ...
Page 124
... PIC18FXX8 NOTES: DS41159E-page 122 © 2006 Microchip Technology Inc. ...
Page 125
... PWM mode Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. module has a Capture special event trigger that can be used as a message received time-stamp for the CAN module (refer to Section 19.0 “CAN Module” for CAN operation) which the ECCP module does not. The ECCP module, on the other hand, has Enhanced PWM functionality and auto-shutdown capability ...
Page 126
... The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Syn- chronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. Interaction © 2006 Microchip Technology Inc. ...
Page 127
... Edge Detect CCP1CON<3:0> Qs Note: I/O pins have diode protection to V © 2006 Microchip Technology Inc. 15.2.5 CAN MESSAGE TIME-STAMP The CAN capture event occurs when a message is received in either of the receive buffers. The CAN module provides a rising edge to the CCP1 module to cause a capture event ...
Page 128
... Note: The special event trigger from the ECCP1 module will not set the Timer1 or Timer3 interrupt flag bits. TMR1H TMR1L Set Flag bit CCP1IF T3CCP1 (PIR1<2>) T3ECCP1 Logic Match and TMR3H TMR3L 0 1 Comparator CCPR1H CCPR1L © 2006 Microchip Technology Inc. ...
Page 129
... T3ECCP1 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. © 2006 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 ...
Page 130
... PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. • OSC (TMR2 Prescale Value) T • (TMR2 Prescale Value) OSC © 2006 Microchip Technology Inc. ...
Page 131
... Shaded cells are not used by PWM and Timer2. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. © 2006 Microchip Technology Inc. 15.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
Page 132
... PIC18FXX8 NOTES: DS41159E-page 130 © 2006 Microchip Technology Inc. ...
Page 133
... PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. The operation of the ECCP module differs from the CCP (discussed in detail in Section 15.0 “Capture/ Compare/PWM (CCP) Modules”) with the addition of an Enhanced PWM module which allows for output channels and user selectable polarity ...
Page 134
... RD5 Configuration ECCP1 RD<5>, 00xx11xx PSP<5> P1A P1B 10xx11xx P1A P1B x1xx11xx ECCP1 MODE – TIMER RESOURCE Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2 RD6 RD7 RD<6>, RD<7>, PSP<6> PSP<7> RD<6>, RD<7>, PSP<6> PSP<7> P1C P1D © 2006 Microchip Technology Inc. ...
Page 135
... Capture/Compare/PWM Register1 (MSB) ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module and Timer1. © 2006 Microchip Technology Inc. 16.3 Compare Mode The Compare mode of the ECCP module is virtually identical in operation to that of the standard CCP module as discussed in Section 15.2 “ ...
Page 136
... Bridge and Full-Bridge Output modes are covered in setting the detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 16-2. ECCP1M<3:0> EPWM1M1<1:0> ECCP1/P1A TRISD<4> P1B TRISD<5> Output Q Controller P1C TRISD<6> P1D TRISD<7> ECCP1DEL ). OSC RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D © 2006 Microchip Technology Inc. ...
Page 137
... P1D Inactive, Active-High P1D Inactive, Active-Low Relationships: • Period = (PR2 + 1) * (TMR2 Prescale Value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = ECCP1DEL OSC © 2006 Microchip Technology Inc. PIC18FXX8 0 Duty Cycle Period Delay Delay PR2 + 1 DS41159E-page 135 ...
Page 138
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as asserted high. V+ FET Driver P1A + Load FET Driver P1B V- V+ FET Driver + - Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2006 Microchip Technology Inc. ...
Page 139
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as asserted high. © 2006 Microchip Technology Inc. PIC18FXX8 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4:7> data latches. The TRISD<4:7> bits must be cleared to make the P1A, P1B, P1C and P1D pins output ...
Page 140
... Use switch drivers that compensate the slow turn off of the power devices. The total turn-off time ( the power device and the driver off must be less than the turn-on time (t QB FET Driver FET Driver © 2006 Microchip Technology Inc. ...
Page 141
... External Switch D Potential Shoot-Through (1) Current Note 1: All signals are shown as active-high the turn-on delay of power switch and driver the turn-off delay of power switch and driver. off © 2006 Microchip Technology Inc. (1) Period ( depending on the Timer2 prescaler OSC OSC OSC Forward Period (PWM) ...
Page 142
... EPDC4 EPDC3 / cycles between the P1A transition and the P1B transition. OSC * W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 EPDC2 EPDC1 EPDC0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 143
... ECCP1DEL EPDC7 EPDC6 EPDC5 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module. © 2006 Microchip Technology Inc. 2. Configure and start TMR2: a) Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit in the PIR1 register. ...
Page 144
... The Auto-Shutdown mode can be manually entered by writing a ‘1’ to the ECCPASE bit. R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 PSSAC0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 145
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2006 Microchip Technology Inc. PIC18FXX8 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported ...
Page 146
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 147
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 ...
Page 148
... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. © 2006 Microchip Technology Inc. ...
Page 149
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2006 Microchip Technology Inc. 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
Page 150
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 1 bit 3 bit 5 bit 4 bit 2 bit 1 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 cycle after Q2 © 2006 Microchip Technology Inc. ...
Page 151
... Interrupt Flag SSPSR to SSPBUF © 2006 Microchip Technology Inc. must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output ...
Page 152
... SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41159E-page 150 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 cycle after Q2 bit 1 bit 0 bit 0 Next Q4 cycle after Q2 © 2006 Microchip Technology Inc. ...
Page 153
... Shaded cells are not used by the MSSP in SPI™ mode. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. © 2006 Microchip Technology Inc. 17.3.10 BUS MODE COMPATIBILITY ...
Page 154
... SSPIF interrupt is set. During transmission, the SSPBUF is not double- Addr Match buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When © 2006 Microchip Technology Inc. ...
Page 155
... In Receive mode Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc MODE) R-0 R-0 R-0 ...
Page 156
... R/W-0 SSPEN CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown © 2006 Microchip Technology Inc. ...
Page 157
... Legend Readable bit -n = Value at POR Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). © 2006 Microchip Technology Inc MODE) R/W-0 R/W-0 R/W-0 R/W-0 ...
Page 158
... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. © 2006 Microchip Technology Inc. ...
Page 159
... The clock must be released by setting bit CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2006 Microchip Technology Inc. PIC18FXX8 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 160
... PIC18FXX8 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS41159E-page 158 © 2006 Microchip Technology Inc. ...
Page 161
... FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX8 DS41159E-page 159 ...
Page 162
... PIC18FXX8 2 FIGURE 17-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS41159E-page 160 © 2006 Microchip Technology Inc. ...
Page 163
... FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX8 DS41159E-page 161 ...
Page 164
... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 17-11). © 2006 Microchip Technology Inc. ...
Page 165
... SDA SCL CKP WR SSPCON1 © 2006 Microchip Technology Inc. assert the SCL line until an external I has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices 2 on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12) ...
Page 166
... PIC18FXX8 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS41159E-page 164 © 2006 Microchip Technology Inc. ...
Page 167
... FIGURE 17-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX8 DS41159E-page 165 ...
Page 168
... UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving data ACK ‘0’ ‘1’ © 2006 Microchip Technology Inc. ...
Page 169
... Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I SDA SDA in SCL SCL in Bus Collision © 2006 Microchip Technology Inc. Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and ...
Page 170
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2006 Microchip Technology Inc. ...
Page 171
... C™ interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2006 Microchip Technology Inc. Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
Page 172
... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h © 2006 Microchip Technology Inc. ...
Page 173
... FIGURE 17-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2006 Microchip Technology Inc. 17.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). ...
Page 174
... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start 1st bit T BRG © 2006 Microchip Technology Inc. ...
Page 175
... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2006 Microchip Technology Inc. PIC18FXX8 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
Page 176
... PIC18FXX8 2 FIGURE 17-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS41159E-page 174 © 2006 Microchip Technology Inc. ...
Page 177
... FIGURE 17-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX8 DS41159E-page 175 ...
Page 178
... SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition later, the PEN bit is BRG WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2006 Microchip Technology Inc. ...
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... BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2006 Microchip Technology Inc. 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software. © 2006 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2006 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S ...
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... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG © 2006 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...
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... SCL PEN BCLIF P SSPIF © 2006 Microchip Technology Inc. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled ...
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... PIC18FXX8 NOTES: DS41159E-page 182 © 2006 Microchip Technology Inc. ...
Page 185
... TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex). ...
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... R = Readable bit -n = Value at POR DS41159E-page 184 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... SREN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2006 Microchip Technology Inc. Example 18-1 shows the calculation of the baud rate error for the following conditions: F Desired Baud Rate = 9600 ...
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... KBAUD ERROR - 185 9.60 0 131 92 19. 74.54 -2. 97.48 +1. 316.80 +5. 422.40 -15. 1267. 255 4.95 - 255 32.768 kHz SPBRG SPBRG value value % (decimal) (decimal) KBAUD ERROR - 0.30 +1.14 26 207 1.17 -2.48 6 103 2.73 +13. 8.20 -14. 8. 255 0.03 - 255 © 2006 Microchip Technology Inc. ...
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... 300 500 HIGH 62. 55.93 LOW 0.24 - 255 0.22 © 2006 Microchip Technology Inc. 33 MHz 25 MHz SPBRG value % % (decimal) ERROR KBAUD ERROR - - -0.07 214 2.40 -0.15 -0.54 53 9.53 -0.76 -0.54 26 19.53 +1.73 -4. ...
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... KBAUD ERROR - - 185 2.40 0 131 46 9. 18.64 -2. 79.20 +3. 105.60 +10. 316.80 +5. 316. 255 1.24 - 255 32.768 kHz SPBRG SPBRG value value % % (decimal) (decimal) KBAUD ERROR 207 0.29 -2. 1.02 -14. 2.05 -14. 2. 255 0.008 - 255 © 2006 Microchip Technology Inc. ...
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... TXEN Baud Rate CLK SPBRG Baud Rate Generator © 2006 Microchip Technology Inc. interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1 register). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register ...
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... Start bit bit 0 Stop bit Word 2 Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u RX9D 0000 000x 0000 000u 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2006 Microchip Technology Inc. ...
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... Baud Rate Generator RC7/RX/DT Pin Buffer and Control SPEN Note: I/O pins have diode protection to V © 2006 Microchip Technology Inc. 18.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. Steps to follow when setting up an Asynchronous Reception with Address Detect Enable: 1 ...
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... POR, BOR Resets 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 000x 0000 000u 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 © 2006 Microchip Technology Inc. ...
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... Shaded cells are not used for synchronous master transmission. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. © 2006 Microchip Technology Inc. software. It will reset only when new data is loaded into the TXREG register. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA register), shows the status of the TSR register ...
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... FIGURE 18-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit DS41159E-page 194 bit 1 bit 2 bit 7 bit 0 Word 1 bit 0 bit 1 bit 2 bit 1 bit 7 Word 2 ‘1’ bit 6 bit 7 © 2006 Microchip Technology Inc. ...
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... RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. © 2006 Microchip Technology Inc. Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 18.1 “USART Baud Rate Generator (BRG)” ...
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... RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing bit CREN. © 2006 Microchip Technology Inc. ...
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... Baud Rate Generator Register Legend unknown unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. © 2006 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 ...
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... PIC18FXX8 NOTES: DS41159E-page 198 © 2006 Microchip Technology Inc. ...