PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 128

• Manufacturer Part Number: PIC18F458T-I/PT
• Description: IC MCU FLASH 16KX16 W/CAN 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3
In Compare mode, the 16-bit CCPR1 and ECCPR1
register value is constantly compared against either the
TMR1 register pair value or the TMR3 register pair
value. When a match occurs, the CCP1 pin can have
one of the following actions:
• Driven high
• Driven low
• Toggle output (high-to-low or low-to-high)
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0. At the same time, interrupt flag
bit CCP1IF is set.
15.3.1
The user must configure the CCP1 pin as an output by
clearing the appropriate TRISC bit.
FIGURE 15-2:
DS41159E-page 126
PIC18FXX8
Note:
Special Event Trigger will:
Compare Mode
CCP1
Note 1:
Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)
Set bit GO/DONE which starts an A/D conversion (ECCP1 only)
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the data latch.
Output Enable
I/O pins have diode protection to V
COMPARE MODE OPERATION BLOCK DIAGRAM
Q
R
S
Special Event Trigger
CCP1CON<3:0>
Mode Select
Output
Logic
DD
Set Flag bit CCP1IF
and V
(PIR1<2>)
Match
SS
.
15.3.2
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
15.3.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets either
the TMR1 or TMR3 register pair. Additionally, the
ECCP1 special event trigger will start an A/D
conversion if the A/D module is enabled.
T3ECCP1
Note:
T3CCP1
TMR1H
TMR1L
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the ECCP1
module will not set the Timer1 or Timer3
interrupt flag bits.
CCPR1H
Comparator
0
© 2006 Microchip Technology Inc.
CCPR1L
1
TMR3H
TMR3L