PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 171

IC MCU FLASH 16KX16 W/CAN 44TQFP

PIC18F458T-I/PT

Manufacturer Part Number
PIC18F458T-I/PT
Description
IC MCU FLASH 16KX16 W/CAN 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F458T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F458T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
17.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 17-17:
TABLE 17-3:
© 2006 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE GENERATOR
2
C™ interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
2
C Master mode, the BRG is
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
SCL
SSPM3:SSPM0
CY
) on the
Control
Reload
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
CLKO
* 2
Reload
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
BRG Down Counter
2
C specification (which applies to rates greater than
SSPADD<6:0>
BRG Value
0Ch
18h
1Fh
63h
09h
27h
02h
09h
00h
F
PIC18FXX8
OSC
(2 Rollovers of BRG)
/4
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
DS41159E-page 169
100kHz
F
SCL
(1)
(1)
(1)
(1)

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