PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 238

• Manufacturer Part Number: PIC18F458T-I/PT
• Description: IC MCU FLASH 16KX16 W/CAN 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 19-9:
19.9
Some requirements for programming of the time
segments:
• Prop Seg + Phase Seg 1
• Phase Seg 2
For example, assume that a 125 kHz CAN baud rate is
desired using 20 MHz for F
a baud rate prescaler value of 04h gives a T
To obtain a nominal bit rate of 125 kHz, the nominal bit
time must be 8 s or 16 T
Using 1 T
gation Segment and 7 T
place the sample point at 10 T
This leaves 6 T
By the rules above, the Sync Jump Width could be the
maximum of 4 T
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
19.10 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
19.11 Bit Timing Configuration
The Configuration registers (BRGCON1, BRGCON2,
BRGCON3) control the bit timing for the CAN bus
interface. These registers can only be modified when
the PIC18FXX8 is in Configuration mode.
DS41159E-page 236
PIC18FXX8
T
Q
Programming Time Segments
Registers
Q
for the Sync Segment, 2 T
Sync
Q
Q
for Phase Segment 2.
Sync Jump Width
. However, normally a large SJW is
SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)
Segment
Q
Q
Prop
for Phase Segment 1 would
.
OSC
Phase Seg 2
. With a T
Q
after the transition.
Q
for the Propa-
OSC
Actual Bit Length
Q
of 500 ns.
Segment 1
of 50 ns,
Phase
Nominal Bit Length
Sample Point
19.11.1
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of multiples of T
19.11.2
The PRSEG bits set the length of the Propagation Seg-
ment in terms of T
Phase Segment 1 in T
many times the RXCAN pin is sampled. Setting this bit
to a ‘1’ causes the bus to be sampled three times; twice
at T
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a ‘1’, then the length of Phase Segment 2 is
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
information processing time (which is fixed at 2 T
the PIC18FXX8).
19.11.3
The PHSEG2<2:0> bits set the length (in T
Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the
SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>
bits have no effect.
Q
/2 before the sample point and once at the normal
BRGCON1
BRGCON2
BRGCON3
Segment 2
Phase
Q
. The SEG1PH bits set the length of
Q
.
© 2006 Microchip Technology Inc.
Q
. The SAM bit controls how
SJW
Q
) of Phase
Q
for