PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 351

• Manufacturer Part Number: PIC18F458T-I/PT
• Description: IC MCU FLASH 16KX16 W/CAN 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 27-13:
TABLE 27-13: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
© 2006 Microchip Technology Inc.
70
71
71A
72
72A
73
73A
74
75
76
78
79
80
Note 1:
Param
No.
Note: Refer to Figure 27-5 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
2:
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TscR
TscF
TscH2doV,
TscL2doV
B
Requires the use of parameter #73A.
Only if parameter #71A and #72A are used.
Symbol
2
B
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
SS
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time
(Master mode)
SCK Output Fall Time (Master mode)
SDO Data Output Valid after
SCK Edge
70
to SCK
80
71
73
MSb In
or SCK
Characteristic
MSb
74
72
Input
75, 76
Continuous
Single Byte
Continuous
Single Byte
PIC18FXX8
PIC18LFXX8
PIC18FXX8
PIC18LFXX8
PIC18FXX8
PIC18LFXX8
Bit 6 - - - - - -1
Bit 6 - - - -1
78
79
1.25 T
1.25 T
1.5 T
Min
T
100
100
CY
LSb
40
40
79
—
—
—
—
—
—
—
—
78
CY
CY
CY
LSb In
+ 40
+ 30
+ 30
PIC18FXX8
Max Units
100
25
45
25
25
45
25
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS41159E-page 349
(Note 1)
(Note 1)
(Note 2)
Conditions