PIC24FJ256DA206-I/PT Microchip Technology, PIC24FJ256DA206-I/PT Datasheet - Page 152

• Manufacturer Part Number: PIC24FJ256DA206-I/PT
• Description: MCU PIC 16BIT FLASH 256K 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA206-I/PT

• Core Size: 16-Bit
• Program Memory Size: 256KB (85.5K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 52
• Ram Memory Size: 96KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ256DA210 FAMILY
TABLE 8-4:
8.6
In addition to the CLKO output (F
certain oscillator modes, the device clock in the
PIC24FJ256DA210 family devices can also be config-
ured to provide a reference clock output signal to a port
pin. This feature is available in all oscillator configura-
tions and allows the user to select a greater range of
clock submultiples to drive external devices in the
application.
This reference clock output is controlled by the
REFOCON register (Register 8-5). Setting the ROEN
bit (REFOCON<15>) makes the clock signal available
on the REFO pin. The RODIV bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
DS39969B-page 152
GCLKDIV<6:0>
Reference Clock Output
0000000
0000001
0000010
0111111
1000000
1000001
1000010
1011111
1100000
1100001
1100010
1111110
1111111
…
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…
DISPLAY MODULE CLOCK FREQUENCY DIVISION
1.25 (start incrementing by 0.25)
OSC
17.5 (start incrementing by 0.5)
34 (start incrementing by 1)
/2) available in
Frequency Divisor
16.75
32.5
1.5
17
18
33
35
63
64
…
…
…
1
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSCI and OSCO, or the current system clock
source, is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on REFO when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT); otherwise, if the POSCEN bit is
not also set, the oscillator on OSCI and OSCO will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
Display Module Clock Frequency
96 MHz Input (48 MHz Input)
76.80 MHz (38.4 MHz)
5.73 MHz (2.86 MHz)
5.65 MHz (2.82 MHz)
5.49 MHz (2.74 MHz)
5.33 MHz (2.66 MHz)
2.95 MHz (1.47 MHz)
2.91 MHz (1.45 MHz)
2.82 MHz (1.41 MHz)
2.74 MHz (1.37 MHz)
1.52 MHz (762 kHz)
1.50 MHz (750 kHz)
96 MHz (48 MHz)
64 MHz (32 MHz)
 2010 Microchip Technology Inc.
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