PIC24FJ256DA206-I/PT Microchip Technology, PIC24FJ256DA206-I/PT Datasheet - Page 314

MCU PIC 16BIT FLASH 256K 64TQFP

PIC24FJ256DA206-I/PT

Manufacturer Part Number
PIC24FJ256DA206-I/PT
Description
MCU PIC 16BIT FLASH 256K 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets

Specifications of PIC24FJ256DA206-I/PT

Core Size
16-Bit
Program Memory Size
256KB (85.5K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC24
No. Of I/o's
52
Ram Memory Size
96KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ256DA206-I/PT
Manufacturer:
AMD
Quantity:
2 100
Part Number:
PIC24FJ256DA206-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24FJ256DA210 FAMILY
REGISTER 22-12: G1W2ADRH: GPU WORK AREA 2 START ADDRESS REGISTER HIGH
REGISTER 22-13: G1PUW: GPU WORK AREA WIDTH REGISTER
REGISTER 22-14: G1PUH: GPU WORK AREA HEIGHT REGISTER
DS39969B-page 314
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-0
W2ADR23
R/W-0
PUW7
R/W-0
PUH7
R/W-0
U-0
U-0
U-0
Unimplemented: Read as ‘0’
PUH<10:0>: GPU Work Area Height bits (in pixels)
Unimplemented: Read as ‘0’
PUW<10:0>: GPU Work Area Width bits (in pixels)
Unimplemented: Read as ‘0’
W2ADR<23:16>: GPU Work Area 2 Start Address High bits
Work area address must point to an even byte address in memory.
W2ADR22
R/W-0
R/W-0
PUW6
PUH6
R/W-0
U-0
U-0
U-0
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W2ADR21
R/W-0
PUH5
R/W-0
PUW5
U-0
R/W-0
U-0
U-0
R/W-0
PUH4
W2ADR20
PUW4
R/W-0
U-0
U-0
R/W-0
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
PUH3
R/W-0
PUW3
W2ADR19
U-0
U-0
R/W-0
U-0
PUH10
PUW10
R/W-0
R/W-0
PUH2
W2ADR18
R/W-0
R/W-0
PUW2
R/W-0
U-0
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
W2ADR17
R/W-0
R/W-0
PUH9
PUH1
R/W-0
PUW9
R/W-0
PUW1
R/W-0
U-0
W2ADR16
R/W-0
R/W-0
PUH8
PUH0
PUW8
PUW0
R/W-0
R/W-0
R/W-0
U-0
bit 8
bit 0
bit 8
bit 0
bit 8
bit 0

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