ST72C215G2M6 STMicroelectronics, ST72C215G2M6 Datasheet - Page 46

• Manufacturer Part Number: ST72C215G2M6
• Description: IC MCU 8BIT 8K FLASH SOIC-28
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72C215G2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3.2 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: ST7
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: ST72C2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDT1-DVP2/US
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition

ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
12.2.3.3 Input Capture
In this section, the index, i , may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected by the
ICAP i pin (see figure 5).
The IC i R register is a read-only register.
The active transition is software programmable
through the IEDG i bit of Control Registers (CR i ).
Timing resolution is one count of the free running
counter: (
Procedure:
To use the input capture function, select the fol-
lowing in the CR2 register:
– Select the timer clock (CC[1:0]) (see
– Select the edge of the active transition on the
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
– Select the edge of the active transition on the
46/140
Clock Control
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as a floating input).
input capture coming from either the ICAP1 pin
or the ICAP2 pin
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as a floating input).
ICiR
f
CPU
/
CC[1:0]).
Bits).
MS Byte
IC i HR
LS Byte
IC i LR
Table 13
When an input capture occurs:
– The ICF i bit is set.
– The IC i R register contains the value of the free
– A timer interrupt is generated if the ICIE bit is set
Clearing the Input Capture interrupt request (i.e.
clearing the ICF i bit) is done in two steps:
1. Reading the SR register while the ICF i bit is set.
2. An access (read or write) to the IC i LR register.
Notes:
1. After reading the IC i HR register, the transfer of
2. The IC i R register contains the free running
3. The 2 input capture functions can be used
4. In One Pulse mode and PWM mode only the
5. The alternate inputs (ICAP1 & ICAP2) are
6. The TOF bit can be used with an interrupt in
running counter on the active transition on the
ICAP i pin (see
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
input capture data is inhibited and ICF i will
never be set until the IC i LR register is also
read.
counter value which corresponds to the most
recent input capture.
together even if the timer also uses the 2 output
compare functions.
input capture 2 function can be used.
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
Moreover if one of the ICAP i pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the IC i HR (see note
1).
order to measure events that exceed the timer
range (FFFFh).
Figure
31).