STM32F101VDT6 STMicroelectronics, STM32F101VDT6 Datasheet - Page 17

MCU ARM 32BIT 384K FLASH 100LQFP

STM32F101VDT6

Manufacturer Part Number
STM32F101VDT6
Description
MCU ARM 32BIT 384K FLASH 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F101VDT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
STM32F101x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
48 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STM3210E-EVAL
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
On-chip Dac
12 bit, 2 Channel
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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STM32F101xC, STM32F101xD, STM32F101xE
2.3.11
2.3.12
2.3.13
2.3.14
Power supply schemes
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
generated when V
than the V
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics
V
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
This regulator is always enabled after reset. It is disabled in Standby mode.
Low-power modes
The STM32F101xC, STM32F101xD and STM32F101xE access line supports three low-
power modes to achieve the best compromise between low power consumption, short
startup time and available wakeup sources:
DD
POR/PDR
/V
V
Provided externally through V
V
and PLL (minimum voltage to be applied to V
and V
V
registers (through power switch) when V
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop modes.
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
DD
SSA
BAT
DDA
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
PVD
and V
power supply and compares it to the V
SSA
DDA
threshold. The interrupt service routine can then generate a warning
must be connected to V
PVD
= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
DD
.
/V
DD
DDA
is below a specified threshold, V
drops below the V
Doc ID 14610 Rev 7
DD
pins.
DD
and V
DD
PVD
SS
is not present.
PVD
threshold and/or when V
DDA
, respectively.
threshold. An interrupt can be
is 2.4 V when the ADC is used). V
Figure 9: Power supply
POR/PDR
, without the need for an
for the values of
DD
/V
DDA
Description
scheme.
is higher
17/106
DDA

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