MCU ARM 32BIT 384K FLASH 100LQFP

STM32F101VDT6

Manufacturer Part NumberSTM32F101VDT6
DescriptionMCU ARM 32BIT 384K FLASH 100LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F101VDT6 datasheet
 


Specifications of STM32F101VDT6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed36MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsDMA, PDR, POR, PVD, PWM, Temp Sensor, WDTNumber Of I /o80
Program Memory Size384KB (384K x 8)Program Memory TypeFLASH
Ram Size48K x 8Voltage - Supply (vcc/vdd)2 V ~ 3.6 V
Data ConvertersA/D 16x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-LQFP
Processor SeriesSTM32F101xCoreARM Cortex M3
Data Bus Width32 bitData Ram Size48 KB
Interface TypeI2C, SPI, USARTMaximum Clock Frequency36 MHz
Number Of Programmable I/os80Number Of Timers6
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2Development Tools By SupplierSTM3210E-EVAL
Minimum Operating Temperature- 40 COn-chip Adc12 bit, 16 Channel
On-chip Dac12 bit, 2 ChannelFeatured ProductSTM32 Cortex-M3 Companion Products
Eeprom Size-For Use With497-10030 - STARTER KIT FOR STM32KSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8505 - KIT STARTER FOR STM32F10XE MCU497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Page 92/106

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Electrical characteristics
Table 57.
DAC characteristics (continued)
Symbol
Parameter
DAC DC current consumption
I
in quiescent mode (Standby
DDVREF+
mode)
DAC DC current consumption
I
in quiescent mode (Standby
DDA
mode)
Differential non linearity
(3)
DNL
Difference between two
consecutive code-1LSB)
Integral non linearity (difference
between measured value at
(3)
INL
Code i and the value at Code i
on a line drawn between Code
0 and last Code 1023)
Offset error
(difference between measured
(3)
Offset
value at Code (0x800) and the
ideal value = V
REF+
(3)
Gain error
Gain error
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
(3)
t
SETTLING
highest input codes when
DAC_OUT reaches final value
±1LSB
Max frequency for a correct
DAC_OUT change when small
(3)
Update rate
variation in the input code (from
code i to i+1LSB)
Wakeup time from off state
(3)
t
(Setting the ENx bit in the DAC
WAKEUP
Control register)
Power supply rejection ratio (to
(2)
PSRR+
V
) (static DC measurement
DDA
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Guaranteed by characterization, not tested in production.
92/106
STM32F101xC, STM32F101xD, STM32F101xE
Min
Typ
Max
220
380
480
±0.5
±2
±1
±4
±10
±3
/2)
±12
±0.5
3
4
1
6.5
10
–67
–40
Doc ID 14610 Rev 7
(1)
Unit
Comments
With no load, worst code
(0xF1C) at V
= 3.6 V in
REF+
µA
terms of DC consumption on
the inputs.
With no load, middle code
µA
(0x800) on the inputs.
With no load, worst code
(0xF1C) at V
= 3.6 V in
REF+
µA
terms of DC consumption on
the inputs.
Given for the DAC in 10-bit
LSB
configuration.
Given for the DAC in 12-bit
LSB
configuration.
Given for the DAC in 10-bit
LSB
configuration.
Given for the DAC in 12-bit
LSB
configuration.
Given for the DAC in 12-bit
mV
configuration.
Given for the DAC in 10-bit at
LSB
V
= 3.6 V.
REF+
Given for the DAC in 12-bit at
LSB
V
= 3.6 V.
REF+
Given for the DAC in 12bit
%
configuration.
 50 pF, R
µs
C
LOAD
LOAD
 50 pF, R
MS/s C
LOAD
LOAD
 50 pF, R
C
LOAD
LOAD
µs
input code between lowest and
highest possible ones.
dB
No R
, C
= 50 pF
LOAD
LOAD
 5 k
 5 k
 5 k