HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 253

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 8.7
Register
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all
1s. MAR and IOAR are not incremented or decremented.
Figure 8.4 illustrates how idle mode operates.
23
23
MAR
All 1s
15
MAR
Register Functions in Idle Mode
ETCR
7
IOAR
0
0
0
Figure 8.4 Operation in Idle Mode
Activated by
SCI0 Receive-
Data-Full
Interrupt
Destination
address
register
Source
address
register
Transfer
counter
1 byte or word is
transferred per request
Function
Transfer
Other
Activation
Source
address
register
Destination
address
register
Transfer
counter
Rev. 3.00 Sep 27, 2006 page 225 of 872
Initial Setting
Destination or
source address
Source or
destination
address
Number of
transfers
Section 8 DMA Controller
REJ09B0325-0300
Operation
Held fixed
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
IOAR