HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 455

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.2.9
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP
Bit 7: G3CMS1
0
1
Bit
Initial value
Read/Write
TPC Output Control Register (TPCR)
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP
15
G3CMS1
to TP )
R/W
Bit 6: G3CMS0
0
1
0
1
7
1
12
G3CMS0
R/W
6
1
Group 2 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 2
(TP
11
G2CMS1
R/W
to TP )
Description
TPC output group 3 (TP
match in ITU channel 0
TPC output group 3 (TP
match in ITU channel 1
TPC output group 3 (TP
match in ITU channel 2
TPC output group 3 (TP
match in ITU channel 3
5
1
8
Section 11 Programmable Timing Pattern Controller
G2CMS0
R/W
4
1
Group 1 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 1
(TP to TP )
G1CMS1
Rev. 3.00 Sep 27, 2006 page 427 of 872
7
R/W
3
1
15
15
15
15
4
G1CMS0
to TP
to TP
to TP
to TP
R/W
15
2
1
to TP
12
12
12
12
) is triggered by compare
) is triggered by compare
) is triggered by compare
) is triggered by compare
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP to TP )
G0CMS1
12
).
R/W
3
1
1
REJ09B0325-0300
(Initial value)
G0CMS0
0
R/W
0
1